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Architectures for Multiplication in Galois Rings
Linköping University, Department of Electrical Engineering.
2004 (English)Independent thesis Basic level (professional degree)Student thesisAlternative title
Arkitekturer för multiplikation i Galois-ringar (Swedish)
Abstract [en]

This thesis investigates architectures for multiplying elements in Galois rings of the size 4^m, where m is an integer.

The main question is whether known architectures for multiplying in Galois fields can be used for Galois rings also, with small modifications, and the answer to that question is that they can.

Different representations for elements in Galois rings are also explored, and the performance of multipliers for the different representations is investigated.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2004. , 73 p.
Series
LiTH-ISY-Ex, 3549
Keyword [en]
Datorteknik, Galois ring, VLSI multiplication, Quaternary codes, Normal basis, Dual basis
Keyword [sv]
Datorteknik
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:liu:diva-2396OAI: oai:DiVA.org:liu-2396DiVA: diva2:19728
Uppsok
teknik
Available from: 2004-07-15 Created: 2004-07-15

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
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More styles
Language
  • de-DE
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  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
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Output format
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