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Author:
Abrahamsson, Björn (Linköping University, Department of Electrical Engineering)
Title:
Architectures for Multiplication in Galois Rings
Alternative title (sv) :
Arkitekturer för multiplikation i Galois-ringar
Department:
Linköping University, Department of Electrical Engineering
Publication type:
Student thesis
Language:
English
Publisher: Institutionen för systemteknik
Level:
Independent thesis Basic level (professional degree)
Undergraduate subject:
Data Transmission
Uppsok:
teknik
Pages:
73
Series:
LiTH-ISY-Ex; 3549
Year of publ.:
2004
URI:
urn:nbn:se:liu:diva-2396
Permanent link:
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2396
Subject category:
Computer Engineering
SVEP category:
Computer engineering
Keywords(en) :
Datorteknik, Galois ring, VLSI multiplication, Quaternary codes, Normal basis, Dual basis
Keywords(sv) :
Datorteknik
Abstract(en) :

This thesis investigates architectures for multiplying elements in Galois rings of the size 4^m, where m is an integer.

The main question is whether known architectures for multiplying in Galois fields can be used for Galois rings also, with small modifications, and the answer to that question is that they can.

Different representations for elements in Galois rings are also explored, and the performance of multipliers for the different representations is investigated.

Available from:
2004-07-15
Created:
2004-07-15
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