A Sizing Algorithm for Non-Overlapping Clock Signal Generators
Independent thesis Basic level (professional degree)Student thesis
The non-overlapping clock signal generator circuits are key elements in switched capacitor circuits since non-overlapping clock signals are generally required. Non-overlapping clock signals means signals running at the same frequency and there is a time between the pulses that none of them is high. This time (when both pulses are logic 0) takes place when the pulses are switching from logic 1 to logic 0 or from logic 0 to logic 1. In this thesis this type of clock signal generators are analyzed and designed for different requirements on the switched capacitor (S/C) circuits. Different analytical models for the delay in CMOS inverters are studied. The clock generators for digital circuits based on phase-locked loop and delay-locked loop are also studied. An algorithm, which can automatically size the non-overlapping clock generator circuits, was implemented.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2004. , 61 p.
Electronics, Non-overlapping clock signal generator circuits, PLL, DLL, CMOS Transistors, Delay models for CMOS circuits
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-2416OAI: oai:DiVA.org:liu-2416DiVA: diva2:19748