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Parallel JPEG Processing with a Hardware Accelerated DSP Processor
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering.
2004 (English)Independent thesis Basic level (professional degree)Student thesisAlternative title
Parallell JPEG-behandling med en hårdvaruaccelerarad DSP processor (Swedish)
Abstract [en]

This thesis describes the design of fast JPEG processing accelerators for a DSP processor.

Certain computation tasks are moved from the DSP processor to hardware accelerators. The accelerators are slave co processing machines and are controlled via a new instruction set. The clock cycle and power consumption is reduced by utilizing the custom built hardware. The hardware can perform the tasks in fewer clock cycles and several tasks can run in parallel. This will reduce the total number of clock cycles needed.

First a decoder and an encoder were implemented in DSP assembler. The cycle consumption of the parts was measured and from this the hardware/software partitioning was done. Behavioral models of the accelerators were then written in C++ and the assembly code was modified to work with the new hardware. Finally, the accelerators were implemented using Verilog.

Extension of the accelerator instructions was given following a custom design flow.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2004. , 108 p.
LiTH-ISY-Ex, 3548
Keyword [en]
Datorteknik, JPEG, JFIF, 2-D DCT, Huffman, Accelerator, HW/SW partitioning
Keyword [sv]
National Category
Computer Engineering
URN: urn:nbn:se:liu:diva-2615OAI: diva2:19951
Available from: 2004-12-06 Created: 2004-12-06

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