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GALS,Design och simulering för FPGA med VHDL
Linköping University, Department of Electrical Engineering.
2004 (Swedish)Independent thesis Basic level (professional degree)Student thesisAlternative title
GALS,Design and simulation for FPGA with VHDL (English)
Abstract [en]

Heat, clock scew and frequency optimization are some of the problems a semiconductor designer must face. By splitting a synchrounous block into multiple pieces which comunicates asynchronously with eachother and provide them with independent clocks, these problems may be reduced.

GALS (Global Asynchronous Local Synchronous) is a wrapper that wraps a synchronous block and provides it with a clock. Multiple GALS-elements will make the whole system. The clockfrequency may be independently adjusted between each block. The clocks may be started and halted independantly depending on the workload.

Describing the system in a hardware language as VHDL, and implement it into an FPGA (Field Programmable Grid Array), makes the development of applications fast and cheap.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2004.
Series
LiTH-ISY-Ex-ET, 3568
Keyword [en]
Electronics, VHDL, GALS, FPGA, Asynchronous, Synthese, Simulation
Keyword [sv]
Elektronik
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-2644OAI: oai:DiVA.org:liu-2644DiVA: diva2:19980
Uppsok
teknik
Available from: 2005-01-03 Created: 2005-01-03

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf