High Speed On-Chip Measurment Circuit
Independent thesis Basic level (professional degree)Student thesisAlternative title
Inbyggd krets för höghastighetsmätning på chip (Swedish)
This master thesis describes a design exploration of a circuit capable of measuring high speed signals without adding significant capacitive load to the measuring node.
It is designed in a 0.13 CMOS process with a supply voltage of 1.2 Volt. The circuit is a master and slave, track-and-hold architecture incorporated with a capacitive voltage divider and a NMOS source follower as input buffer to protect the measuring node and increase the input voltage range.
This thesis presents the implementation process and the theory needed to understand the design decisions and consideration throughout the design. The results are based on transistor level simulations performed in Cadence Spectre.
The results show that it is possible to observe the analog behaviour of a high speed signal by down converting it to a lower frequency that can be brought off-chip. The trade off between capacitive load added to the measuring node and input bandwidth of the measurment circuit is also presented.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2005.
Electronics, CMOS, 0.13, sampling, periodic sampling, digital oscilloscope, time equivalent sampling, track and hold, master and slave, sampling clock generator, voltagedivider, source follower, sampling switch, transmission gate, RLC-line
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-2764ISRN: LITH-ISY-EX--3599--SEOAI: oai:DiVA.org:liu-2764DiVA: diva2:20106