Design Optimization of Time- and Cost-Constrained Fault-Tolerant Embedded Systems With Checkpointing and Replication
2009 (English)In: IEEE Transactions on VLSI Systems, ISSN 1063-8210 , Vol. 17, no 3, 389-402 p.Article in journal (Refereed) Published
We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes and communications are statically scheduled. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that multiple transient faults are tolerated and the timing constraints of the application are satisfied. We present several design optimization approaches which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example.
Place, publisher, year, edition, pages
2009. Vol. 17, no 3, 389-402 p.
Fault tolerance, processor scheduling, real time systems, redundancy
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-17155DOI: 10.1109/TVLSI.2008.2003166OAI: oai:DiVA.org:liu-17155DiVA: diva2:202145