Improved implementation of a 1K FFT with low power consumption
Independent thesis Basic level (professional degree)Student thesis
In this master thesis, a behavioral VHDL model of a 1k Fast Fourier Transform (FFT) algorithm has been improved, first to make it synthesizable and second to obtain a low power consumption. The purpose of the thesis has not been to focus on the FFT algorithm itself or the theory behind it. Instead the aim has been to document and motivate the necessary modifications, to reach the stated requirements, and to discuss the results. The thesis is divided into sections so that the design flow closely can be followed from the initial FFT, down to the final architecture. The two major design steps covered are synthesis and power simulation. The synthesis process has been the most time consuming part of the thesis.
The synthesis tool Cadence Ambit PKS was used. Throughout the synthesis, the modifications and solutions will be discussed and comparisons are continuously made between the different solutions and the initial FFT. The best solution will then be the starting point in the next design step, which is simulation of the design with respect to power consumption. This is done by using a simulation tool from Synopsys called NanoSim. Also here, every solution is tested and compared to each other, followed by a concluding discussion. The technology used to implement the design is a 0.35um CMOS process.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2005.
Electronics, FFT, synthesis, low power, VHDL.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-2881ISRN: LITH-ISY-EX--05/3737--SEOAI: oai:DiVA.org:liu-2881DiVA: diva2:20223