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VHDL Implementation of a Fast Adder Tree
Linköping University, Department of Electrical Engineering.
2005 (English)Independent thesis Basic level (professional degree), 20 points / 30 hpStudent thesis
Abstract [en]

This thesis discusses the design and implementation of a VHDL generator for Wallace tree with (3:2) counter modules and (2:2) counter modules to solve fast addition problem.

The basic research has been carried out by MATLAB programming environment and automatic generation of VHDL file based on the result obtained from MATLAB simulation. MODELSIM has been used for compilation and simulation of the VHDL file.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2005. , 92 p.
Keyword [en]
Wallace tree, counter module, simulation, generator, add tree, cell array
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-3838ISRN: LiTH-ISY-EX--05/3760--SEOAI: oai:DiVA.org:liu-3838DiVA: diva2:20456
Uppsok
teknik
Supervisors
Examiners
Available from: 2005-09-16 Created: 2005-09-16

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fulltext(1113 kB)14976 downloads
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258a40d2de281e5355b1d375de701deb9d9482833bb0c1fb90a38bd9ca600e9f24189f21
Type fulltextMimetype application/pdf

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
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More styles
Language
  • de-DE
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Output format
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