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A study of CABAC hardware acceleration with configurability in multi-standard media processing
Linköping University, Department of Electrical Engineering.
2005 (English)Independent thesis Basic level (professional degree), 20 points / 30 hpStudent thesisAlternative title
En studie i konfigurerbar hårdvaruaccelerering för CABAC i flerstandards mediabearbetning (Swedish)
Abstract [en]

To achieve greater compression ratios new video and image CODECs like H.264 and JPEG 2000 take advantage of Context adaptive binary arithmetic coding. As it contains computationally heavy algorithms, fast implementations have to be made when they are performed on large amount of data such as compressing high resolution formats like HDTV. This document describes how entropy coding works in general with a focus on arithmetic coding and CABAC. Furthermore the document dicusses the demands of the different CABACs and propose different options to hardware and instruction level optimisation. Testing and benchmarking of these implementations are done to ease evaluation. The main contribution of the thesis is parallelising and unifying the CABACs which is discussed and partly implemented. The result of the ILA is improved program flow through a specialised branching operations. The result of the DHA is a two bit parallel accelerator with hardware sharing between JPEG 2000 and H.264 encoder with limited decoding support.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2005. , 90 p.
Keyword [en]
CABAC, Arithmetic coding, H.264, JPEG 2000, instruction level optimizing, accelerators, assembler, VLC, encoder, hardware reuse, profiling, DSP, multimedia
National Category
Computer Engineering
URN: urn:nbn:se:liu:diva-4477ISRN: LITH-ISY-EX--05/3788--SEOAI: diva2:20631
Available from: 2005-10-24 Created: 2005-10-24

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