liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Design and implementation of a hardware unit for complex division
Linköping University, Department of Electrical Engineering.
2005 (English)Independent thesis Basic level (professional degree), 20 points / 30 hpStudent thesis
Abstract [en]

The purpose of the thesis was to investigate and evaluate existing algorithms for division of complex numbers. The investigation should include implementation of a few suitable algorithms in VHDL. The main application for the divider is compensation for fading in a baseband processor.

Since not much public research is done within the area of complex division in hardware, a divider based on real valued division was designed. The design only implements inversion of complex numbers instead of complete division because it is simpler and the application does not need full division, thus the required chip size is reduced.

An examination of the different kinds of algorithms that exists for real valued division was done and two of the methods were found suitable for implementation, digit recurrence and functional iteration. From each of the two classes of algorithms one algorithm was chosen and implemented in VHDL. Two different versions of the inverter were designed for each method, one with full throughput and one with half throughput. The implementations show very similar results in terms of speed, size and performance. For most cases however, the digit recurrence implementation has a slight advantage.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2005. , 59 p.
Keyword [en]
Hardware, Division, Complex, Arithmetics, ASIC
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:liu:diva-5427ISRN: LITH-ISY-EX--05/3724--SEOAI: oai:DiVA.org:liu-5427DiVA: diva2:21307
Uppsok
teknik
Supervisors
Examiners
Available from: 2006-01-13 Created: 2006-01-13

Open Access in DiVA

fulltext(320 kB)1587 downloads
File information
File name FULLTEXT01.pdfFile size 320 kBChecksum MD5
702dc13a0b1c54c5dc98905d6b46aab458f97ad8a873c3d8bc3d69ed3cb1096164ed3b4f
Type fulltextMimetype application/pdf

By organisation
Department of Electrical Engineering
Computer Engineering

Search outside of DiVA

GoogleGoogle Scholar
Total: 1587 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

urn-nbn

Altmetric score

urn-nbn
Total: 777 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf