High-Level Test Generation and Built-In Self-Test Techniques for Digital Systems
2002 (English)Licentiate thesis, monograph (Other academic)
The technological development is enabling production of increasingly complex electronic systems. All those systems must be verified and tested to guarantee correct behavior. As the complexity grows, testing is becoming one of the most significant factors that contribute to the final product cost. The established low-level methods for hardware testing are not any more sufficient and more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. This thesis reports on one such work that deals in particular with high-level test generation and design for testability techniques.
The contribution of this thesis is twofold. First, we investigate the possibilities of generating test vectors at the early stages of the design cycle, starting directly from the behavioral description and with limited knowledge about the final implementation architecture. We have developed for this purpose a novel hierarchical test generation algorithm and demonstrated the usefulness of the generated tests not only for manufacturing test but also for testability analysis.
The second part of the thesis concentrates on design for testability. As testing of modern complex electronic systems is a very expensive procedure, special structures for simplifying this process can be inserted into the system during the design phase. We have proposed for this purpose a novel hybrid built-in self-test architecture, which makes use of both pseudorandom and deterministic test patterns, and is appropriate for modern system-on-chip designs. We have also developed methods for optimizing hybrid built-in self-test solutions and demonstrated the feasibility and efficiency of the proposed technique.
Place, publisher, year, edition, pages
Institutionen för datavetenskap , 2002. , 102 p.
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 973
Digital technique, electronic systems, test vectors, testability, built-in self-test architecture
IdentifiersURN: urn:nbn:se:liu:diva-5728ISBN: 91-7373-442-XOAI: oai:DiVA.org:liu-5728DiVA: diva2:21483
2002-10-14, 00:00 (English)
Report code: LiU-Tek-Lic-2002:46.2002-11-052002-11-052009-05-20