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A 0.5-6 GHz Low Gain RF Front-End for Low-IF Over-Sampling Receivers in 90nm CMOS
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
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2009 (English)Manuscript (Other academic)
Abstract [en]

The software defined radio concept has emerged as a feasible solution for future multigand and multistandard receivers. The proposed software defined radio architecture needs a front-end with moderate or low gain, high linearity, and low noise figure. This paper presents the design and measurement results of low gain RF front-end in 90nm CMOS covering the frequency range of 0.5-6GHz. The front-end is a modified form of a balanced active mixer to enhance its gain and achieve wideband input matching. The transcjonductance stage of a mixer is split into NMOS-PMOS inverter pair for better linearity and partial noise cancellation. The inverter stage with common drain feedback achieves wideband input impedance match getter than -8dB up to 8GHz. The front-end achieves voltage conversion gain of 5dB at 6GHz with 3dB bandwidth of more than 5.5GHz. The measured single side band noise figure at LO frequency of 1.5GHz and IF of 30MHz is 7dB. The measured 1dB compression point is -17dBm at 2.4GHz at 1GHz. The complete front-end consumers 23mW with active chip area of only 0.048mm2.

Place, publisher, year, edition, pages
2009.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-18196OAI: oai:DiVA.org:liu-18196DiVA: diva2:216691
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2010-01-14Bibliographically approved
In thesis
1. Flexible Wireless Receivers: On-Chip Testing Techniques and Design for Testability
Open this publication in new window or tab >>Flexible Wireless Receivers: On-Chip Testing Techniques and Design for Testability
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In recent years the interest in the design of low cost multistandard mobile devices has gone from technical aspiration to the commercial reality. Usually, the emerging wireless applications prompt the conception of new wireless standards. The end user wants to access voice, data, and streaming media using a single wireless terminal. In RF perspective, these standards differ in frequency band, sensitivity, data rate, bandwidth, and modulation type. Therefore, a flexible multistandard radio receiver covering most of the cellular, WLAN, and short range communication standards in 800MHz to 6GHz band is highly desired. To keep the cost low, high level of integration becomes a necessity for the multistandard flexible radio.

Due to aggressive CMOS scaling the fT of the transistors has surpassed the value of 200 GHz. Moreover, as the CMOS technology has proven to be the best suited for monolithic integration, therefore it seems to be the future choice for the physical implementation of such a flexible receiver. In this thesis, two multiband sampling radio receiver front-ends implemented in 130 nm and 90 nm CMOS including test circuitry (DfT) are presented that is one step ahead in this direction.

In modern radio transceivers the estimated cost of testing is a significant portion of manufacturing cost and is escalating with every new generation of RF chips. In order to reduce the test cost it is important to identify the faulty circuits very early in the design flow, even before packaging. In this thesis, on-chip testing techniques to reduce the test time and cost are presented. For integrated RF transceivers the chip reconfiguration by loopback setup can be used. Variants including the bypassing technique to improve testability and to enable on-chip test when the direct loopback is not feasible are presented. A technique for boosting the testability by the elevated symbol error rate test (SER) is also presented. It achieves better sensitivity and shorter test time compared to the standard SER test.

Practical DfT implementation is addressed by circuit level design of various test blocks such as a linear attenuator, stimulus generator, and RF detectors embedded in RF chips without notable performance penalty. The down side of CMOS scaling is the increase in parameter variability due to process variations and mismatch. Both the test circuitry (DfT) and the circuit under test (CUT) are affected by these variations. A new calibration scheme for the test circuitry to compensate this effect is presented. On-chip DC measurements supported by a statistical regression method are used for this purpose.

Wideband low-reflection PCB transmission lines are needed to enable the functional RF testing using external signal generators for RF chips directly bonded on the PCB. Due to extremely small chip dimensions it is not possible to layout the transmission line without width discontinuity. A step change in the substrate thickness is utilized to cancel this effect thus resulting in the low-reflection transmission line.

In summary, all of these techniques at the system and circuit level pave a way to new opportunities towards low-cost transceiver testing, especially in volume production.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2009. 105 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1261
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18208 (URN)978-91-7393-601-9 (ISBN)
Public defence
2009-06-03, C3, C-huset, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2009-09-17Bibliographically approved
2. Reconfigurable and Broadband Circuits for Flexible RF Front Ends
Open this publication in new window or tab >>Reconfigurable and Broadband Circuits for Flexible RF Front Ends
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Most of today’s microwave circuits are designed for specific function and special need. There is a growing trend to have flexible and reconfigurable circuits. Circuits that can be digitally programmed to achieve various functions based on specific needs. Realization of high frequency circuit blocks that can be dynamically reconfigured to achieve the desired performance seems to be challenging. However, with recent advances in many areas of technology these demands can now be met.

Two concepts have been investigated in this thesis. The initial part presents the feasibility of a flexible and programmable circuit (PROMFA) that can be utilized for multifunctional systems operating at microwave frequencies. Design details and PROMFA implementation is presented. This concept is based on an array of generic cells, which consists of a matrix of analog building blocks that can be dynamically reconfigured. Either each matrix element can be programmed independently or several elements can be programmed collectively to achieve a specific function. The PROMFA circuit can therefore realize more complex functions, such as filters or oscillators. Realization of a flexible RF circuit based on generic cells is a new concept. In order to validate the idea, two test chips have been fabricated. The first chip implementation was carried out in a 0.2μm GaAs process, ED02AH from OMMICTM. The second chip was implemented in a standard 90nm CMOS process. Simulated and measured results are presented along with some key applications such as low noise amplifier, tunable band pass filter and a tunable oscillator.

The later part of the thesis covers the design and implementation of broadband RF front-ends that can be utilized for multistandard terminals such as software defined radio (SDR). The concept of low gain, highly linear frontends has been presented. For proof of concept two test chips have been implemented in 90nm CMOS technology process. Simulated and measurement results are presented. These RF front-end implementations utilize wideband designs with active and passive mixer configurations.

We have also investigated narrowband tunable LNAs. A dual band tunable LNA MMIC has been fabricated in 0.2μm GaAs process. A self tuning technique has been proposed for the optimization of this LNA.

Place, publisher, year, edition, pages
Link: Linköping University Electronic Press, 2009. 82 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1259
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18512 (URN)978-91-7393-605-7 (ISBN)
Public defence
2009-08-25, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Available from: 2009-05-29 Created: 2009-05-29 Last updated: 2009-05-29Bibliographically approved

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Ramzan, RashadAhsan, NaveedFritzin, JonasDabrowski, Jerzy Svensson, Christer

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