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Boosting SER Test for RF Transceivers by Simple DSP Technique
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
2007 (English)In: DATE '07 Design, Automation & Test in Europe Conference & Exhibition, 2007., IEEE , 2007, 1-6 p.Conference paper, Published paper (Refereed)
Abstract [en]

The paper presents a new technique of symbol error rate test (SER) for RF transceivers. A simple DSP algorithm implemented at the receiver baseband is introduced in terms of constellation correction, which is usually used to compensate for IQ imbalance. The test is oriented at detection of impairments in gain and noise figure in a transceiver frontend. The proposed approach is shown to enhance the sensitivity of a traditional SER test to the limits of its counterpart, the error vector magnitude (EVM) test. Its advantage over EVM is in simple implementation, lower DSP overhead and the ability of achieving a larger dynamic range of the test response. Also the test time is saved compared to a traditional SER test. The technique is validated by a simulation model of a Wi-Fi transceiver implemented in MatlabTM.

Place, publisher, year, edition, pages
IEEE , 2007. 1-6 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-18197DOI: 10.1109/DATE.2007.364680ISBN: 978-3-9810801-2-4 (print)OAI: oai:DiVA.org:liu-18197DiVA: diva2:216695
Conference
IEEE Design Automation and Test in Europe Conference (DATE), Acropolis, Nice, France, 16-20 April
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2013-11-22Bibliographically approved
In thesis
1. Flexible Wireless Receivers: On-Chip Testing Techniques and Design for Testability
Open this publication in new window or tab >>Flexible Wireless Receivers: On-Chip Testing Techniques and Design for Testability
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In recent years the interest in the design of low cost multistandard mobile devices has gone from technical aspiration to the commercial reality. Usually, the emerging wireless applications prompt the conception of new wireless standards. The end user wants to access voice, data, and streaming media using a single wireless terminal. In RF perspective, these standards differ in frequency band, sensitivity, data rate, bandwidth, and modulation type. Therefore, a flexible multistandard radio receiver covering most of the cellular, WLAN, and short range communication standards in 800MHz to 6GHz band is highly desired. To keep the cost low, high level of integration becomes a necessity for the multistandard flexible radio.

Due to aggressive CMOS scaling the fT of the transistors has surpassed the value of 200 GHz. Moreover, as the CMOS technology has proven to be the best suited for monolithic integration, therefore it seems to be the future choice for the physical implementation of such a flexible receiver. In this thesis, two multiband sampling radio receiver front-ends implemented in 130 nm and 90 nm CMOS including test circuitry (DfT) are presented that is one step ahead in this direction.

In modern radio transceivers the estimated cost of testing is a significant portion of manufacturing cost and is escalating with every new generation of RF chips. In order to reduce the test cost it is important to identify the faulty circuits very early in the design flow, even before packaging. In this thesis, on-chip testing techniques to reduce the test time and cost are presented. For integrated RF transceivers the chip reconfiguration by loopback setup can be used. Variants including the bypassing technique to improve testability and to enable on-chip test when the direct loopback is not feasible are presented. A technique for boosting the testability by the elevated symbol error rate test (SER) is also presented. It achieves better sensitivity and shorter test time compared to the standard SER test.

Practical DfT implementation is addressed by circuit level design of various test blocks such as a linear attenuator, stimulus generator, and RF detectors embedded in RF chips without notable performance penalty. The down side of CMOS scaling is the increase in parameter variability due to process variations and mismatch. Both the test circuitry (DfT) and the circuit under test (CUT) are affected by these variations. A new calibration scheme for the test circuitry to compensate this effect is presented. On-chip DC measurements supported by a statistical regression method are used for this purpose.

Wideband low-reflection PCB transmission lines are needed to enable the functional RF testing using external signal generators for RF chips directly bonded on the PCB. Due to extremely small chip dimensions it is not possible to layout the transmission line without width discontinuity. A step change in the substrate thickness is utilized to cancel this effect thus resulting in the low-reflection transmission line.

In summary, all of these techniques at the system and circuit level pave a way to new opportunities towards low-cost transceiver testing, especially in volume production.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2009. 105 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1261
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18208 (URN)978-91-7393-601-9 (ISBN)
Public defence
2009-06-03, C3, C-huset, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2009-09-17Bibliographically approved
2. Flexible wireless receivers: on-chip testing techniques and design for test
Open this publication in new window or tab >>Flexible wireless receivers: on-chip testing techniques and design for test
2008 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

In recent years the interest in the design of low cost multistandard mobile devices has gone from technical aspiration to commercial essential. Usually, the emerging wireless applications prompt the conception of new wireless standards. The end user wants to access voice, data, and streaming media from single wireless terminal. In RF perspective, these standards differ in frequency band, sensiti vity, data rate, bandwidth, and modulation type. Therefore, a reconfigurable multistandard radio receiver covering most of the cellular, WLAN and short range standards (800MHz-6GHz band) is required. To keep the cost low, high level of integration becomes a necessity for multistandard radio.

Recently, due to aggressive CMOS scaling ƒT of the transistors has reached the value of hundred of GHz. Moreover, CMOS technology is best suited for monolithic integration, so it seems to be the future choice for the realization of such a reconfigurable multistandard receiver. In this thesis, a multiband sampling radio receiver front-end with test circuitry (Off) implemented in 0.13μm CMOS is presented, which is one step ahead in this direction.

In modem radio transceivers, the estimated cost of testing is a significant portion of manufacturing cost and is escalating with every new generation of RF transceivers. In order to reduce the test cost it is important to identify the faulty circuits very early in the design flow even before packaging. In this thesis, two onchip testing techniques to reduce the test time and cost are presented. The first addresses an offset loopback test for integrated RF transceivers which are not suitable for direct loopback. The other is a new technique for symbol error rate test (SER) that is better in sensitivity and test time compared to traditional SER test.

The down side of CMOS scaling is the increase in parameter variability due to process variations and mismatch. Both the test circuitry (Off) and circuit under test (CUT) are affected by these variations. In order to compensate the impact of large process variations on Off circuitry, a new calibration scheme using DC on-chip measurements supported by Artificial Neural Networks (ANN) as a statistical regression method is presented.

Place, publisher, year, edition, pages
Linköping: Linköpings universitet, 2008. 96 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1378
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-43570 (URN)74243 (Local ID)978-91-7393-816-7 (ISBN)74243 (Archive number)74243 (OAI)
Presentation
2008-09-09, Glashuset, Linköpings Universitet, Linköping, 00:00 (Swedish)
Opponent
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-11-22

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