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Built-in Loopback Test for IC RF Transceivers
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
2010 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, Vol. 18, no 6, 933-946 p.Article in journal (Refereed) Published
Abstract [en]

The essentials of the on-chip loopback test for integrated RF transceivers are presented. The available on-chip baseband processor serves as a tester while the RF front-end is under test enabled by on-chip test attenuator and in some cases by an offset mixer, too. Various system-level tests, like BER, EVM or spectral measurements are discussed. By using this technique in mass production, the RF test equipment can be largely avoided and the test cost reduced. Different variants of the loopback setup including the bypassing technique and RF detectors to boost the chip testability are considered. The existing limitations and tradeoffs are discussed in terms of test feasibility, controllability, and observability versus the chip performance. The fault-oriented approach supported by sensitization technique is put in contrast to the functional test. Also the impact of production tolerances is addressed in terms of a simple statistical model and the detectability thresholds. The paper is based on the present and previous work of the authors, largely revised and upgraded to provide a comprehensive description of the on-chip loopback test. Simulation examples of practical communication transceivers such as WLAN and EDGE under test are also included.

Place, publisher, year, edition, pages
2010. Vol. 18, no 6, 933-946 p.
Keyword [en]
Built-in self test (BiST), design for testability (DfT), loopback test, on-chip test, RF test, RF transceivers, structural test
National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-18198DOI: 10.1109/TVLSI.2009.2019085ISI: 000278435900008OAI: diva2:216698
©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Jerzy Dabrowski and Rashad Ramzan, Built-in Loopback Test for IC RF Transceivers, 2010, IEEE Transactions on Very Large Scale Integration (vlsi) Systems, (18), 6, 933-946. Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2010-06-24Bibliographically approved
In thesis
1. Flexible Wireless Receivers: On-Chip Testing Techniques and Design for Testability
Open this publication in new window or tab >>Flexible Wireless Receivers: On-Chip Testing Techniques and Design for Testability
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In recent years the interest in the design of low cost multistandard mobile devices has gone from technical aspiration to the commercial reality. Usually, the emerging wireless applications prompt the conception of new wireless standards. The end user wants to access voice, data, and streaming media using a single wireless terminal. In RF perspective, these standards differ in frequency band, sensitivity, data rate, bandwidth, and modulation type. Therefore, a flexible multistandard radio receiver covering most of the cellular, WLAN, and short range communication standards in 800MHz to 6GHz band is highly desired. To keep the cost low, high level of integration becomes a necessity for the multistandard flexible radio.

Due to aggressive CMOS scaling the fT of the transistors has surpassed the value of 200 GHz. Moreover, as the CMOS technology has proven to be the best suited for monolithic integration, therefore it seems to be the future choice for the physical implementation of such a flexible receiver. In this thesis, two multiband sampling radio receiver front-ends implemented in 130 nm and 90 nm CMOS including test circuitry (DfT) are presented that is one step ahead in this direction.

In modern radio transceivers the estimated cost of testing is a significant portion of manufacturing cost and is escalating with every new generation of RF chips. In order to reduce the test cost it is important to identify the faulty circuits very early in the design flow, even before packaging. In this thesis, on-chip testing techniques to reduce the test time and cost are presented. For integrated RF transceivers the chip reconfiguration by loopback setup can be used. Variants including the bypassing technique to improve testability and to enable on-chip test when the direct loopback is not feasible are presented. A technique for boosting the testability by the elevated symbol error rate test (SER) is also presented. It achieves better sensitivity and shorter test time compared to the standard SER test.

Practical DfT implementation is addressed by circuit level design of various test blocks such as a linear attenuator, stimulus generator, and RF detectors embedded in RF chips without notable performance penalty. The down side of CMOS scaling is the increase in parameter variability due to process variations and mismatch. Both the test circuitry (DfT) and the circuit under test (CUT) are affected by these variations. A new calibration scheme for the test circuitry to compensate this effect is presented. On-chip DC measurements supported by a statistical regression method are used for this purpose.

Wideband low-reflection PCB transmission lines are needed to enable the functional RF testing using external signal generators for RF chips directly bonded on the PCB. Due to extremely small chip dimensions it is not possible to layout the transmission line without width discontinuity. A step change in the substrate thickness is utilized to cancel this effect thus resulting in the low-reflection transmission line.

In summary, all of these techniques at the system and circuit level pave a way to new opportunities towards low-cost transceiver testing, especially in volume production.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2009. 105 p.
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1261
National Category
Engineering and Technology
urn:nbn:se:liu:diva-18208 (URN)978-91-7393-601-9 (ISBN)
Public defence
2009-06-03, C3, C-huset, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2009-09-17Bibliographically approved

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