CMOS blocks for on-chip RF test
2006 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 49, no 2, 151-150 p.Article in journal (Refereed) Published
In this paper we present two designs of CMOS blocks suitable for integration with RF frontend blocks for test purposes. Those are a programmable RF test attenuator and a reconfigurable low noise amplifier (LNA), optimized with respect to their function and location in the circuit. We discuss their performances in terms of the test- and normal operation mode. The presented application model aims at a transceiver under loopback test with enhanced controllability and detectability. The circuits are designed for 0.35μm CMOS process. Simulation results of the receiver frontend operating in 2.4 GHz band are presented showing tradeoffs between the performance and test functionality.
Place, publisher, year, edition, pages
Springer Link , 2006. Vol. 49, no 2, 151-150 p.
RF test, Loopback test, DfT, Radio transceivers, RF-CMOS design, RF frontend
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-18199DOI: 10.1007/s10470-006-9615-2OAI: oai:DiVA.org:liu-18199DiVA: diva2:216700