On-Chip Stimulus Generator in 90nm CMOS for Gain, Linearity, and Blocking Profile Test of Wideband RF Front-ends
(English)Manuscript (Other academic)
This paper presents the design and measurement of a stimulus generator suitable for on-chip RF test aimed at gain, 1dB-CP, and the blocking profile measurement. Implemented in 90 nm CMOS the generator consists of two low-noise voltage controlled ring oscillators (VCOs) and an adder. It can generate a single or two-tone signal in range of 0.9–5.6 GHz with tone spacing of 3 MHz to 4.5 GHz and adjustable output power. The VCOs are based on symmetrically loaded double differential delay line architecture. The measured phase noise is -80dBc/Hz at an offset frequency of 1MHz for the oscillation frequency of 2.4 GHz. A single VCO consumes 26mW at 1 Ghz while providing -10dBm power into 50Ω load. The silicon area of the complete test circuit including coupling capacitors is only 0.03 mm2. The measured gain, 1dB-CP, and blocking profile of the wideband receiver using the on-chip stimulus generator are within ±8%, ±10%, and ±18% of their actual values, respectively. These error values are acceptable for making pass or fail decision during production testing.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-18200OAI: oai:DiVA.org:liu-18200DiVA: diva2:216703