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Flexible Wireless Receivers: On-Chip Testing Techniques and Design for Testability
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In recent years the interest in the design of low cost multistandard mobile devices has gone from technical aspiration to the commercial reality. Usually, the emerging wireless applications prompt the conception of new wireless standards. The end user wants to access voice, data, and streaming media using a single wireless terminal. In RF perspective, these standards differ in frequency band, sensitivity, data rate, bandwidth, and modulation type. Therefore, a flexible multistandard radio receiver covering most of the cellular, WLAN, and short range communication standards in 800MHz to 6GHz band is highly desired. To keep the cost low, high level of integration becomes a necessity for the multistandard flexible radio.

Due to aggressive CMOS scaling the fT of the transistors has surpassed the value of 200 GHz. Moreover, as the CMOS technology has proven to be the best suited for monolithic integration, therefore it seems to be the future choice for the physical implementation of such a flexible receiver. In this thesis, two multiband sampling radio receiver front-ends implemented in 130 nm and 90 nm CMOS including test circuitry (DfT) are presented that is one step ahead in this direction.

In modern radio transceivers the estimated cost of testing is a significant portion of manufacturing cost and is escalating with every new generation of RF chips. In order to reduce the test cost it is important to identify the faulty circuits very early in the design flow, even before packaging. In this thesis, on-chip testing techniques to reduce the test time and cost are presented. For integrated RF transceivers the chip reconfiguration by loopback setup can be used. Variants including the bypassing technique to improve testability and to enable on-chip test when the direct loopback is not feasible are presented. A technique for boosting the testability by the elevated symbol error rate test (SER) is also presented. It achieves better sensitivity and shorter test time compared to the standard SER test.

Practical DfT implementation is addressed by circuit level design of various test blocks such as a linear attenuator, stimulus generator, and RF detectors embedded in RF chips without notable performance penalty. The down side of CMOS scaling is the increase in parameter variability due to process variations and mismatch. Both the test circuitry (DfT) and the circuit under test (CUT) are affected by these variations. A new calibration scheme for the test circuitry to compensate this effect is presented. On-chip DC measurements supported by a statistical regression method are used for this purpose.

Wideband low-reflection PCB transmission lines are needed to enable the functional RF testing using external signal generators for RF chips directly bonded on the PCB. Due to extremely small chip dimensions it is not possible to layout the transmission line without width discontinuity. A step change in the substrate thickness is utilized to cancel this effect thus resulting in the low-reflection transmission line.

In summary, all of these techniques at the system and circuit level pave a way to new opportunities towards low-cost transceiver testing, especially in volume production.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press , 2009. , 105 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1261
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-18208ISBN: 978-91-7393-601-9 (print)OAI: oai:DiVA.org:liu-18208DiVA: diva2:216737
Public defence
2009-06-03, C3, C-huset, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2009-09-17Bibliographically approved
List of papers
1. A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS
Open this publication in new window or tab >>A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS
2007 (English)In: IEEE International Solid State Circuits Conference (ISSCC), San Francisco, California, USA, Februrary 11-15, IEEE , 2007, 424-613 p.Conference paper, Published paper (Refereed)
Abstract [en]

A 1.4V wideband inductorless LNA, implemented in a 0.13mum CMOS process, consumes 25mW and occupies 0.019mm2. Measurement results show 17dB voltage gain, 7GHz BW, 2.4dB NF at 3GHz, -4.1 dBm IIP3, and -20dBm P1dB. A common-drain feedback circuit provides wideband 50Omega input matching and partial noise cancellation. A current reuse technique improves both gain and power.

Place, publisher, year, edition, pages
IEEE, 2007
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18193 (URN)10.1109/ISSCC.2007.373475 (DOI)1-4244-0852-0 (ISBN)
Conference
IEEE International Solid-State Circuits Conference (ISSCC 2007)
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2013-11-18Bibliographically approved
2. Multiband RF-Sampling Receiver Front-End with On-Chip Testability in 0.13μm CMOS
Open this publication in new window or tab >>Multiband RF-Sampling Receiver Front-End with On-Chip Testability in 0.13μm CMOS
2009 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 61, no 2, 115-127 p.Article in journal (Refereed) Published
Abstract [en]

In this paper a flexible RF-sampling front-end primarily intended for WLAN standards operating in the 2.4 GHz and 5–6 GHz bands is presented. The circuit is implemented with on-chip Design for Test (DfT) features in 0.13 μm CMOS process. The front-end consists of a wideband LNA, a sampling IQ down-converter implemented as switched-capacitor decimation filter, test attenuator (TA), and RF detectors. The architecture is generic and scalable in frequency. It can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz with 29 subsampling. The selectable decimation factor of 8 or 16 makes the A/D conversion feasible. The frequency response, linearity, and NF of the whole frontend have been measured. The power consumption of complete RF front-end is 176 mW. The on-chip DfT features are helpful in reduction of overall test cost and time in volume production. The measurement results show the feasibility of DfT approach for multiband radio receiver design using standard CMOS process.

Place, publisher, year, edition, pages
Springer Link, 2009
Keyword
DfT, Sampling receiver, Wideband RF front-end, Wideband LNA, Multiband receiver, Multi-standard receiver
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18195 (URN)10.1007/s10470-009-9286-x (DOI)
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2017-12-13Bibliographically approved
3. A 0.5-6 GHz Low Gain RF Front-End for Low-IF Over-Sampling Receivers in 90nm CMOS
Open this publication in new window or tab >>A 0.5-6 GHz Low Gain RF Front-End for Low-IF Over-Sampling Receivers in 90nm CMOS
Show others...
2009 (English)Manuscript (Other academic)
Abstract [en]

The software defined radio concept has emerged as a feasible solution for future multigand and multistandard receivers. The proposed software defined radio architecture needs a front-end with moderate or low gain, high linearity, and low noise figure. This paper presents the design and measurement results of low gain RF front-end in 90nm CMOS covering the frequency range of 0.5-6GHz. The front-end is a modified form of a balanced active mixer to enhance its gain and achieve wideband input matching. The transcjonductance stage of a mixer is split into NMOS-PMOS inverter pair for better linearity and partial noise cancellation. The inverter stage with common drain feedback achieves wideband input impedance match getter than -8dB up to 8GHz. The front-end achieves voltage conversion gain of 5dB at 6GHz with 3dB bandwidth of more than 5.5GHz. The measured single side band noise figure at LO frequency of 1.5GHz and IF of 30MHz is 7dB. The measured 1dB compression point is -17dBm at 2.4GHz at 1GHz. The complete front-end consumers 23mW with active chip area of only 0.048mm2.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18196 (URN)
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2010-01-14Bibliographically approved
4. Boosting SER Test for RF Transceivers by Simple DSP Technique
Open this publication in new window or tab >>Boosting SER Test for RF Transceivers by Simple DSP Technique
2007 (English)In: DATE '07 Design, Automation & Test in Europe Conference & Exhibition, 2007., IEEE , 2007, 1-6 p.Conference paper, Published paper (Refereed)
Abstract [en]

The paper presents a new technique of symbol error rate test (SER) for RF transceivers. A simple DSP algorithm implemented at the receiver baseband is introduced in terms of constellation correction, which is usually used to compensate for IQ imbalance. The test is oriented at detection of impairments in gain and noise figure in a transceiver frontend. The proposed approach is shown to enhance the sensitivity of a traditional SER test to the limits of its counterpart, the error vector magnitude (EVM) test. Its advantage over EVM is in simple implementation, lower DSP overhead and the ability of achieving a larger dynamic range of the test response. Also the test time is saved compared to a traditional SER test. The technique is validated by a simulation model of a Wi-Fi transceiver implemented in MatlabTM.

Place, publisher, year, edition, pages
IEEE, 2007
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18197 (URN)10.1109/DATE.2007.364680 (DOI)978-3-9810801-2-4 (ISBN)
Conference
IEEE Design Automation and Test in Europe Conference (DATE), Acropolis, Nice, France, 16-20 April
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2013-11-22Bibliographically approved
5. Built-in Loopback Test for IC RF Transceivers
Open this publication in new window or tab >>Built-in Loopback Test for IC RF Transceivers
2010 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 18, no 6, 933-946 p.Article in journal (Refereed) Published
Abstract [en]

The essentials of the on-chip loopback test for integrated RF transceivers are presented. The available on-chip baseband processor serves as a tester while the RF front-end is under test enabled by on-chip test attenuator and in some cases by an offset mixer, too. Various system-level tests, like BER, EVM or spectral measurements are discussed. By using this technique in mass production, the RF test equipment can be largely avoided and the test cost reduced. Different variants of the loopback setup including the bypassing technique and RF detectors to boost the chip testability are considered. The existing limitations and tradeoffs are discussed in terms of test feasibility, controllability, and observability versus the chip performance. The fault-oriented approach supported by sensitization technique is put in contrast to the functional test. Also the impact of production tolerances is addressed in terms of a simple statistical model and the detectability thresholds. The paper is based on the present and previous work of the authors, largely revised and upgraded to provide a comprehensive description of the on-chip loopback test. Simulation examples of practical communication transceivers such as WLAN and EDGE under test are also included.

Keyword
Built-in self test (BiST), design for testability (DfT), loopback test, on-chip test, RF test, RF transceivers, structural test
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18198 (URN)10.1109/TVLSI.2009.2019085 (DOI)000278435900008 ()
Note
©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Jerzy Dabrowski and Rashad Ramzan, Built-in Loopback Test for IC RF Transceivers, 2010, IEEE Transactions on Very Large Scale Integration (vlsi) Systems, (18), 6, 933-946. http://dx.doi.org/10.1109/TVLSI.2009.2019085 Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2017-12-13Bibliographically approved
6. CMOS blocks for on-chip RF test
Open this publication in new window or tab >>CMOS blocks for on-chip RF test
2006 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 49, no 2, 151-150 p.Article in journal (Refereed) Published
Abstract [en]

In this paper we present two designs of CMOS blocks suitable for integration with RF frontend blocks for test purposes. Those are a programmable RF test attenuator and a reconfigurable low noise amplifier (LNA), optimized with respect to their function and location in the circuit. We discuss their performances in terms of the test- and normal operation mode. The presented application model aims at a transceiver under loopback test with enhanced controllability and detectability. The circuits are designed for 0.35μm CMOS process. Simulation results of the receiver frontend operating in 2.4 GHz band are presented showing tradeoffs between the performance and test functionality.

Place, publisher, year, edition, pages
Springer Link, 2006
Keyword
RF test, Loopback test, DfT, Radio transceivers, RF-CMOS design, RF frontend
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18199 (URN)10.1007/s10470-006-9615-2 (DOI)
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2017-12-13Bibliographically approved
7. On-Chip Stimulus Generator in 90nm CMOS for Gain, Linearity, and Blocking Profile Test of Wideband RF Front-ends
Open this publication in new window or tab >>On-Chip Stimulus Generator in 90nm CMOS for Gain, Linearity, and Blocking Profile Test of Wideband RF Front-ends
(English)Manuscript (Other academic)
Abstract [en]

This paper presents the design and measurement of a stimulus generator suitable for on-chip RF test aimed at gain, 1dB-CP, and the blocking profile measurement. Implemented in 90 nm CMOS the generator consists of two low-noise voltage controlled ring oscillators (VCOs) and an adder. It can generate a single or two-tone signal in range of 0.9–5.6 GHz with tone spacing of 3 MHz to 4.5 GHz and adjustable output power. The VCOs are based on symmetrically loaded double differential delay line architecture. The measured phase noise is -80dBc/Hz at an offset frequency of 1MHz for the oscillation frequency of 2.4 GHz. A single VCO consumes 26mW at 1 Ghz while providing -10dBm power into 50Ω load. The silicon area of the complete test circuit including coupling capacitors is only 0.03 mm2. The measured gain, 1dB-CP, and blocking profile of the wideband receiver using the on-chip stimulus generator are within ±8%, ±10%, and ±18% of their actual values, respectively. These error values are acceptable for making pass or fail decision during production testing.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18200 (URN)
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2010-01-14Bibliographically approved
8. CMOS RF/DC Voltage Detector for on-Chip Test
Open this publication in new window or tab >>CMOS RF/DC Voltage Detector for on-Chip Test
2006 (English)In: IEEE International Multitopic Conference (INMIC), Islamabad, Pakistan, December 23-24, IEEE , 2006, 472-476 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we present a framework for RF testing of a radio front-end using CMOS RF/DC voltage detectors connected between RF nodes and a DC test bus. The detector is designed and implemented in 0.13mum CMOS process and it achieves high input impedance, low power, small area and wide dynamic range. Measurement results show that internal RF nodes can be accessed without significantly degrading the chip performance. A verification procedure using an extra DC bus is proposed to verify that due to process variations all detectors are within an acceptable performance limit.

Place, publisher, year, edition, pages
IEEE, 2006
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18201 (URN)10.1109/INMIC.2006.358213 (DOI)1-4244-0795-8 (ISBN)
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2009-05-11Bibliographically approved
9. On-chip calibration of RF detectors by DC stimuli and artificial neural networks
Open this publication in new window or tab >>On-chip calibration of RF detectors by DC stimuli and artificial neural networks
2008 (English)In: Proceedings of 2008 IEEE Radio Frequency Integrated Circuits Symposium, Piscataway, N.J, USA: IEEE , 2008, 571-574 p.Conference paper, Published paper (Refereed)
Abstract [en]

In the nanometer regime, especially the RF and analog circuits exhibit wide parameter variability, and consequently every chip produced needs to be tested. On-chip design for testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, artificial neural networks (ANN) are employed as multivariate regression technique to architect a general RF calibration scheme using DC- instead of RF stimuli. This relaxes the routing requirements on a chip for GHz test signals along with the reduction in test time and cost. The RF detector, a key element of a radio front-end DfT circuitry, designed in 65 nm CMOS is used to demonstrate the calibration scheme.

Place, publisher, year, edition, pages
Piscataway, N.J, USA: IEEE, 2008
Series
IEEE Radio Frequency Integrated Circuits Symposium. Digest of Papers, ISSN 1529-2517
Keyword
ANN application, On-chip RF detector, RF BIST, RF DfT, RF calibration, RF testing
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18202 (URN)10.1109/RFIC.2008.4561502 (DOI)978-1-4244-1808-4 (ISBN)978-1-4244-1809-1 (ISBN)
Conference
IEEE Radio Frequency Integrated Circuits Symposium, Atlanta, GA, USA, June 15-17 2008
Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2014-03-25Bibliographically approved
10. Wideband Low Reflection Transmission Lines for Bare Chip on Multilayer PCB
Open this publication in new window or tab >>Wideband Low Reflection Transmission Lines for Bare Chip on Multilayer PCB
2011 (English)In: ETRI Journal, ISSN 1225-6463, E-ISSN 2233-7326, Vol. 33, no 3, 335-343 p.Article in journal (Refereed) Published
Abstract [en]

The pad pitch of modern RF ICs is in order of few tens of micrometers. Connecting the large number of high speed I/Os to outside world with good signal fidelity and low cost is extremely challenging. To cope with this requirement, we need reflection-free transmission lines from on-chip pad to on-board SMA connectors. Such a transmission line is very hard to design due to the difference in on-chip and on-board feature size and the requirement for extremely large bandwidth. In this paper, we propose the use of narrow tracks close to chip and wide tracks away from the chip. This narrow to wide transition in width results in impedance discontinuity. A step change in substrate thickness is utilized to cancel the effect of the width discontinuity, thus achieving a reflection-free microstrip. To verify the concept several microstrips were designed on multilayer FR4 PCB without any additional manufacturing steps. The TDR measurements reveal that impedance variation is less then 3Ω for 50Ω microstrip when the width changes from 165μm to 940μm and substrate thickness changes from 100μm to 500μm. The Sparameter measurement on same microstrip shows S11 better then -9dB for the frequency range 1-6GHz.

Place, publisher, year, edition, pages
Daejeon, Korea: Electronics and Telecommunications Research Institute, 2011
Keyword
Bare chip mounting, RF testing, microstrip discontinuities, microstrip transitions.
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-18203 (URN)10.4218/etrij.11.0110.0386 (DOI)
Note

The original status of this article was: Manuscript.

Available from: 2009-05-11 Created: 2009-05-11 Last updated: 2017-12-13Bibliographically approved

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