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Design and Evaluation of an Ultra-Low Power Successive Approximation ADC
Linköping University, Department of Electrical Engineering.
2009 (English)Independent thesis Advanced level (degree of Master (Two Years)), 30 credits / 45 HE creditsStudent thesis
Abstract [en]

Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC.This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13μm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR ADC combines a capacitive DAC with S/H circuit, uses a binary-weighted capacitor array for the DAC and utilizes a dynamic latch comparator. Evaluation results show that at a supply voltage of 1.2V and an output rate of 1kS/s, the SAR ADC performs a total power consumption of 103nW and a signal-to-noise-and-distortion ratio of 54.4dB. Proper performance is achieved down to a supply voltage of 0.45V, with a power consumption of 16nW.

Place, publisher, year, edition, pages
2009. , 70 p.
Keyword [en]
Analog-to-digital converter (ADC), charge redistribution, CMOS, low power, low supply voltage, successive approximation, latched comparator
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:liu:diva-18219ISRN: LiTH-ISY-EX--09/4176--SEOAI: diva2:216811
Subject / course
Electronic Devices
Systemet, Entrance 27, Huset B, Linkoping University (English)
Available from: 2009-05-14 Created: 2009-05-12 Last updated: 2011-10-18Bibliographically approved

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Zhang, Dai
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