Design of Highly Linear Sampling Switches for CMOS Track-and-Hold Circuits
Independent thesis Basic level (professional degree), 20 points / 30 hpStudent thesis
This thesis discusses non-linearities associated with a sampling switch and compares transmission gate, bootstrapping and bulk-effect compensation architectures at circuit level from linearity point of view for 0.35 um CMOS process. All switch architectures have been discussed and designed with an additional constraint of switch reliability.
Results indicate that for a specified supply of 3.3 Volts, bulk-effect compensation does not improve third-order harmonic distortion significantly which defines the upper most limit on linearity for a differential topology. However, for low-voltage operations bulk-effect compensation improves third-order harmonic noticeably.
Place, publisher, year, edition, pages
Universitetsbibliotek , 2006. , 66 p.
Switch non-linearities, Bootstrap switch, Bulk-effect compensation switch, Charge injection
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-6339ISRN: LiTH-ISY-EX--06/3827--SEOAI: oai:DiVA.org:liu-6339DiVA: diva2:21768
2006-04-21, Nollstället, B, 581 83,Linköping University, Linköping, Sweden, 10:15