Pulse Width Modulation for On-chip Interconnects
Independent thesis Basic level (professional degree), 20 points / 30 hpStudent thesis
With an increasing number of transistors integrated on a single die, the need for global on-chip interconnectivity is growing. Long interconnects, in turn, have very large capacitances which consume a large share of a chip’s total power budget.
Power consumption can be lowered in several ways, mainly by reduction of switching activity, reduction of total capacitance and by using low voltage swing. In this project, the issue is addressed by proposing a new encoding based on Pulse Width Modulation (PWM). The implementation of this encoding will both lower the switching activity and decrease the capacitance between nearby wires. Hence, the total effective capacitance will be reduced considerably. Schematic level implementation of a robust transmitter and receiver circuit was carried out in CMOS090, designed for speeds up to 100 MHz. On a 10 mm wire, this implementation would give a 40% decrease in power dissipation compared to a parallel bus having the same metal footprint. The proposed encoding can be efficiently applied for global interconnects in sub-micron systems-on-chip (SoC).
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2005. , 107 p.
Low-power, Interconnect, On-chip, Delay line, Pulse width modulation, Phase coding
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-6341ISRN: LiTH-ISY-EX--05/3688--SEOAI: oai:DiVA.org:liu-6341DiVA: diva2:21770
2005-12-05, Systemet, B-huset, Campus Valla, Linköpings universitet, Linköping, 13:15