Design of a High Speed AGC Amplifier for Multi-level Coding
Independent thesis Advanced level (degree of Magister), 20 points / 30 hpStudent thesis
This thesis presents the design of a broadband and high speed dc-coupled AGC amplifier for multi-level (4-PAM) signaling with a symbol rate of 1-GS/s ( 2-Gb/s ) . It is a high frequency analog design with several design challenges such as high -3 dB bandwidth ( greater than 500 MHz ) and highly linear gain while accommodating a large input swing range ( 120 mVp-p to 1800 mVp-p diff.) and delivering constant
differential output swing of 1700 mVp-p to 50-ohm off-chip loads at high speed. Moreover, the gain control circuit has been designed in analog domain. The amplifier incorporates both active and passive feedback in shunt-shunt topology in order to achieve wide bandwidth. This standalone chip has been implemented in AMS 0.35 micron CMOS process. The post layout eye-diagrams seem to be quite satisfactory.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2006. , 86 p.
Broadband amplifier, high speed amplifier, 4-PAM Signaling, multi-level signaling, AGC amplifier, automatic gain control, shunt-shunt feedback, wideband amplifier
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-6509ISRN: LiTH-ISY-EX--06/3803--SEOAI: oai:DiVA.org:liu-6509DiVA: diva2:21847
2006-05-19, Algorithmen, B huset, 10:00