A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS
2012 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 70, no 1, 79-90 p.Article in journal (Refereed) Published
This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves high linearity in a wide band (0.5-6GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8dB up to 6GHz. The measured single sideband noise figure at an LO frequency of 2GHz and an IF of 10MHz is 6.25dB. The front-end achieves a voltage conversion gain of 4.5dB at 1GHz with 3dB bandwidth of more than 6GHz. The measured input referred 1dB compression point is +1.5dBm while the IIP3 is +11.73dBm and the IIP2 is +26.23dBm respectively at an LO frequency of 2GHz. The RF front-end consumes 6.2mW from a 1.1V supply with an active chip area of 0.0856mm2.
Place, publisher, year, edition, pages
SpringerLink , 2012. Vol. 70, no 1, 79-90 p.
Blocker suppression, common gate (CG), highly linear, low power, multi-standard, software defined radio, wideband front-end
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-18511DOI: 10.1007/s10470-011-9667-9ISI: 000298604100007OAI: oai:DiVA.org:liu-18511DiVA: diva2:220094
The original status of this article was: Manuscript.2009-05-292009-05-292012-01-27Bibliographically approved