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Two-Tone PLL  for On-Chip Test In 90nm-Technology
Linköping University, Department of Electrical Engineering.
2009 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

In this report the two-tone PLL circuit intended for on-chip test of RF blocks is presented. The primary application is the third order intermodulation test (TOI), vital for RF front-ends. If the spectral analysis can also be completed by DSP available on the chip or on board, it provides a built in self-test (BiST) which can replace costly test instrumentation (ATE). The advantage of the designed two-tone PLL is that it practically prevents the locking effect while keeping the two oscillation frequencies close. Also by careful design the possible intermodulation distortion of the two-tone stimulus can be avoided.

The two-tone PLL has been designed and verified at the system level using Verilog-A models in Cadence TM. Besides, two building blocks of the PLL were implemented at the circuit level in 90nm CMOS technology. The obtained results are promising in terms of a practical two-tone BiST implementation.

Place, publisher, year, edition, pages
2009. , 75 p.
Keyword [en]
System -On-Chip
National Category
Information Science
URN: urn:nbn:se:liu:diva-18590ISRN: LiTH-ISY--EX--09/4311--SEOAI: diva2:220552
Algoritmen, B-house, Campus Valla, Linköpings universitet, Linköping (English)
Available from: 2009-06-10 Created: 2009-06-01 Last updated: 2009-06-10Bibliographically approved

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