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RTL implementation of Viterbi Decoder
Linköping University, Department of Electrical Engineering.
2006 (English)Student paper first term, 20 points / 30 hpStudent thesis
Abstract [en]

A forward error correction technique known as convolutional coding with Viterbi decoding was explored in this final thesis. This Viterbi project is part of the baseband Error control project at electrical engineering department, Linköping University.

In this project, the basic Viterbi decoder behavior model was built and simulated. The convolutional encoder, puncturing, 3 bit soft decision, BPSK and AWGN channel were implemented in MATLAB code. The BER was tested to evaluate the decoding performance.

The main issue of this thesis is to implement the RTL level model of Viterbi decoder. With the testing results of behavior model, with minimizing the data path, register size and butterflies in the design, we try to achieve a low silicon cost design. The RTL Viterbi decoder model includes the Branch Metric block, the Add-Compare-Select block, the trace-back block, the decoding block and next state block. With all done, we further understand about the Viterbi decoding algorithm and the DSP implementation methods.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2006. , 69 p.
Keyword [en]
baseband FEC Viterbi Decoding
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:liu:diva-6949ISRN: LiTH-ISY-EX--06/3886--SEOAI: oai:DiVA.org:liu-6949DiVA: diva2:22064
Presentation
2006-06-02, Nollstället, Hus B, S-581 83 Linköping, SWEDEN, Linköping University, 13:00
Uppsok
teknik
Supervisors
Examiners
Available from: 2006-06-22 Created: 2006-06-22

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf