In this thesis it is investigated if representing a field Zp, p = 1 (mod 4) prime, by another field Z[i]/ < a + bi > over the gaussian integers, with p = a2 + b2, results in arithmetic architectures using a smaller number of logic gates. Only bit parallell architectures are considered and the programs Espresso and SIS are used for boolean minimization of the architectures. When counting gates only NAND, NOR and inverters are used.

Two arithmetic operations are investigated, addition and multiplication. For addition the architecture over Z[i]/ < a+bi > uses a significantly greater number of gates compared with an architecture over Zp. For multiplication the architecture using gaussian integers uses a few less gates than the architecture over Zp for p = 5 and for p = 17 and only a few more gates when p = 13. Only the values 5, 13, 17 have been compared for multiplication. For addition 12 values, ranging from 5 to 525313, have been compared.

It is also shown that using a blif model as input architecture to SIS yields much better performance, compared to a truth table architecture, when minimizing.