High Bandwidth, Low-Latency Global Interconnect
2003 (English)In: VLSI Circuits and Systems, Proceedings of the SPIE, Vol. 5117, Gran Canaria, Spain, May, 2003, 126-134 p.Conference paper (Other academic)
Global interconnects have been identified as a serious limitation to chip scaling, due to their limited bandwidth and large delay. A critical analysis of intrinsic limitations of electrical interconnect indicates that these limitations can be overcome. This basic analysis is presented, together with design constraints. We demonstrate a scheme for this, based on the utilization of upper-level metals as transmission lines. A global communication architecture based on a global mesochronous, local synchronous approach allows very high data-rate per wire and therefore very high bandwidth in buses of limited width. As an example, we demonstrate a 320µm wide bus with a capacity of 160Gb/s in a nearly standard 0.18µm process.
Place, publisher, year, edition, pages
2003. 126-134 p.
interconnect, low latency, high bandwidth, global
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-13907DOI: 10.1117/12.499957OAI: oai:DiVA.org:liu-13907DiVA: diva2:22179