Well-Behaved Global On-Chip Interconnect
2005 (English)In: IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1057-7122, Vol. 52, no 2, 318-323 p.Article in journal (Refereed) Published
Global interconnects have been identified as a serious limitation to chip scaling, due to their latency and power consumption. We demonstrate a scheme to overcome these limitations, based on the utilization of upper-level metals, combined with structured communication architecture. Microwave style transmission lines in upper-level metals allow close-to-velocity-of-light delays if properly dimensioned. As an example, we demonstrate a 480-μm-wide and 20-mm-long bus with a capacity of 320 Gb/s in a nearly standard 0.18-μm process. The process differs from a standard process only through a somewhat thicker outer metal layer. We further illustrate how "self pre-emphasis" at the launch of a data pulse can be used to double the maximum available data rate over a wire. The proposed techniques are scalable, given that higher level metals are properly dimensioned in future processes.
Place, publisher, year, edition, pages
2005. Vol. 52, no 2, 318-323 p.
interconnect, global interconnect, interconnect delay, on-chip bus, upper-level metal
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-13911DOI: 10.1109/TCSI.2004.840483OAI: oai:DiVA.org:liu-13911DiVA: diva2:22183