Capacitive Crosstalk Effects on On-Chip Interconnect Latencies and Data-Rates
2005 (English)In: Proceedings of the 23rd Norchip Conference, Oulu, Finland, 2005, 281-284 p.Conference paper (Other academic)
We investigate how crosstalk affects latency, data-rate, and power dissipation for on-chip global interconnects in a 6-layer 0.18μm CMOS process. A simplified analytical interconnect description is compared to circuit simulations of a field solver extracted wire model. We show how repeater insertion can be utilized to achieve wave pipelining, which pushes maximum data-rate beyond the classical limit. Compared to simulations, the analytical model is pessimistic by 10% for latency, 30% for maximum data-rate, and 35% for power dissipation, highlighting the importance of avoiding too simple wire representations.
Place, publisher, year, edition, pages
2005. 281-284 p.
CMOS integrated circuits, circuit simulation, crosstalk, integrated circuit interconnections, integrated circuit modelling, 0.18 micron, CMOS process, capacitive crosstalk effects, circuit simulations, data-rate, on-chip interconnect latencies, power dissipation, wave pipelining
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-13913DOI: 10.1109/NORCHP.2005.1597044OAI: oai:DiVA.org:liu-13913DiVA: diva2:22185