An On-Chip Delay- and Skew-Insensitive Multi-Cycle Comunication Scheme
2006 (English)In: International Solid-State Circuits Conference 2006, San Fransisco, USA, 2006Conference paper (Other academic)
A synchronous latency-insensitive design (SLID) method that mitigates unknown on-chip global wire delays and removes the need for controlling global clock skew is presented. An SLID-based 5.4mm-long on-chip global bus, fabricated in a standard 0.18mum CMOS process, supports 3Gb/s/wire and accepts plusmn2 clock cycles of data-clock skew. This paper focuses on data synchronization for large global on-chip signals, which has become a difficult issue in high-frequency processor designs.
Place, publisher, year, edition, pages
CMOS integrated circuits, delays, integrated circuit design, integrated circuit interconnections, synchronisation, 0.18 micron, 5.4 mm, CMOS process, data synchronization, data-clock skew, global clock skew, multicycle communication, on-chip global wire delays, synchronous latency-insensitive design
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-13914DOI: 10.1109/ISSCC.2006.1696233ISBN: 1-4244-0079-1OAI: oai:DiVA.org:liu-13914DiVA: diva2:22186