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Efficient high-speed on-chip global interconnects
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2006 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The continuous miniaturization of integrated circuits has opened the path towards System-on-Chip realizations. Process shrinking into the nanometer regime improves transistor performancewhile the delay of global interconnects, connecting circuit blocks separated by a long distance, significantly increases. In fact, global interconnects extending across a full chip can have a delay corresponding to multiple clock cycles. At the same time, global clock skew constraints, not only between blocks but also along the pipelined interconnects, become even tighter. On-chip interconnects have always been considered RC-like, that is exhibiting long RC-delays. This has motivated large efforts on alternatives such as on-chip optical interconnects, which have not yet been demonstrated, or complex schemes utilizing on-chip F-transmission or pulsed current-mode signaling.

In this thesis, we show that well-designed electrical global interconnects, behaving as transmission lines, have the capacity of very high data rates (higher than can be delivered by the actual process) and support near velocity-of-light delay for single-ended voltage-mode signaling, thus mitigating the RC-problem. We critically explore key interconnect performance measures such as data delay, maximum data rate, crosstalk, edge rates and power dissipation. To experimentally demonstrate the feasibility and superior properties of on-chip transmission line interconnects, we have designed and fabricated a test chip carrying a 5 mm long global communication link. Measurements show that we can achieve 3 Gb/s/wire over the 5 mm long, repeaterless on-chip bus implemented in a standard 0.18 μm CMOS process, achieving a signal velocity of 1/3 of the velocity of light in vacuum.

To manage the problems due to global wire delays, we describe and implement a Synchronous Latency Insensitive Design (SLID) scheme, based on source-synchronous data transfer between blocks and data re-timing at the receiving block. The SLIDtechnique not onlymitigates unknown globalwire delays, but also removes the need for controlling global clock skew. The high-performance and high robustness capability of the SLID-method is practically demonstrated through a successful implementation of a SLID-based, 5.4 mm long, on-chip global bus, supporting 3 Gb/s/wire and dynamically accepting ± 2 clock cycles of data-clock skew, in a standard 0.18 μm CMOS porcess.

In the context of technology scaling, there is a tendency for interconnects to dominate chip power dissipation due to their large total capacitance. In this thesis we address the problem of interconnect power dissipation by proposing and analyzing a transition-energy cost model aimed for efficient power estimation of performancecritical buses. The model, which includes properties that closely capture effects present in high-performance VLSI buses, can be used to more accurately determine the energy benefits of e.g. transition coding of bus topologies. We further show a power optimization scheme based on appropriate choice of reduced voltage swing of the interconnect and scaling of receiver amplifier. Finally, the power saving impact of swing reduction in combination with a sense-amplifying flip-flop receiver is shown on a microprocessor cache bus architecture used in industry.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2006.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 992
Keyword [en]
Microelectronics, Global Interconnects, On-Chip Interconnects, Velocity-of-Light Delay, On-Chip Communication, Low-Latency, Transmission Lines
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-7123ISBN: 91-85457-87-6 (print)OAI: oai:DiVA.org:liu-7123DiVA: diva2:22187
Public defence
2006-01-27, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2006-07-18 Created: 2006-07-18
List of papers
1. Low-Power, Low-Latency Global Interconnect
Open this publication in new window or tab >>Low-Power, Low-Latency Global Interconnect
2002 (English)In: Proceedings of the IEEE ASIC/SOC Conference, Rochester, USA, 2002, 394-398 p.Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13906 (URN)
Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2009-05-07
2. High Bandwidth, Low-Latency Global Interconnect
Open this publication in new window or tab >>High Bandwidth, Low-Latency Global Interconnect
2003 (English)In: VLSI Circuits and Systems, Proceedings of the SPIE, Vol. 5117, Gran Canaria, Spain, May, 2003, 126-134 p.Conference paper, Published paper (Other academic)
Abstract [en]

Global interconnects have been identified as a serious limitation to chip scaling, due to their limited bandwidth and large delay. A critical analysis of intrinsic limitations of electrical interconnect indicates that these limitations can be overcome. This basic analysis is presented, together with design constraints. We demonstrate a scheme for this, based on the utilization of upper-level metals as transmission lines. A global communication architecture based on a global mesochronous, local synchronous approach allows very high data-rate per wire and therefore very high bandwidth in buses of limited width. As an example, we demonstrate a 320µm wide bus with a capacity of 160Gb/s in a nearly standard 0.18µm process.

Keyword
interconnect, low latency, high bandwidth, global
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13907 (URN)10.1117/12.499957 (DOI)
Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2009-06-05
3. A Low-swing Single-ended L1 Cache Bus Technique for Sub-90 nm Technologies
Open this publication in new window or tab >>A Low-swing Single-ended L1 Cache Bus Technique for Sub-90 nm Technologies
Show others...
2004 (English)In: Proceedings of the European Solid-State Circuits Conference, Leuven, Belgium, 2004, 475-477 p.Conference paper, Published paper (Other academic)
Keyword
global interconnect, low-swing signalling
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13908 (URN)
Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2009-05-07
4. An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies
Open this publication in new window or tab >>An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies
Show others...
2004 (English)In: Proceedings of the Power and Timing Modeling, Optimization and Simulation Conference, Santorini, Greece, 2004, 849-858 p.Conference paper, Published paper (Other academic)
Keyword
Transition energy cost model, power estimation, on-chip interconnect
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13909 (URN)
Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2009-05-07
5. High-Speed On-Chip Interconnect Modeling for Circuit Simulation
Open this publication in new window or tab >>High-Speed On-Chip Interconnect Modeling for Circuit Simulation
2004 (English)In: Proceedings of the Norchip Conference, Oslo, Norway, November, 2004, 143-146 p.Conference paper, Published paper (Other academic)
Keyword
on-chip interconnect modeling, global interconnect, lossy trnsmission lines, signal integrity
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13910 (URN)10.1109/NORCHP.2004.1423843 (DOI)
Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2009-05-07
6. Well-Behaved Global On-Chip Interconnect
Open this publication in new window or tab >>Well-Behaved Global On-Chip Interconnect
2005 (English)In: IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1057-7122, Vol. 52, no 2, 318-323 p.Article in journal (Refereed) Published
Abstract [en]

Global interconnects have been identified as a serious limitation to chip scaling, due to their latency and power consumption. We demonstrate a scheme to overcome these limitations, based on the utilization of upper-level metals, combined with structured communication architecture. Microwave style transmission lines in upper-level metals allow close-to-velocity-of-light delays if properly dimensioned. As an example, we demonstrate a 480-μm-wide and 20-mm-long bus with a capacity of 320 Gb/s in a nearly standard 0.18-μm process. The process differs from a standard process only through a somewhat thicker outer metal layer. We further illustrate how "self pre-emphasis" at the launch of a data pulse can be used to double the maximum available data rate over a wire. The proposed techniques are scalable, given that higher level metals are properly dimensioned in future processes.

Keyword
interconnect, global interconnect, interconnect delay, on-chip bus, upper-level metal
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13911 (URN)10.1109/TCSI.2004.840483 (DOI)
Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2010-03-16
7. A 3 Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency
Open this publication in new window or tab >>A 3 Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency
2006 (English)In: Proceedings of the International Conference on VLSI Design 2006, Hyderabad, India, 2006, 117-122 p.Conference paper, Published paper (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13912 (URN)
Available from: 2006-07-18 Created: 2006-07-18
8. Capacitive Crosstalk Effects on On-Chip Interconnect Latencies and Data-Rates
Open this publication in new window or tab >>Capacitive Crosstalk Effects on On-Chip Interconnect Latencies and Data-Rates
2005 (English)In: Proceedings of the 23rd Norchip Conference, Oulu, Finland, 2005, 281-284 p.Conference paper, Published paper (Other academic)
Abstract [en]

We investigate how crosstalk affects latency, data-rate, and power dissipation for on-chip global interconnects in a 6-layer 0.18μm CMOS process. A simplified analytical interconnect description is compared to circuit simulations of a field solver extracted wire model. We show how repeater insertion can be utilized to achieve wave pipelining, which pushes maximum data-rate beyond the classical limit. Compared to simulations, the analytical model is pessimistic by 10% for latency, 30% for maximum data-rate, and 35% for power dissipation, highlighting the importance of avoiding too simple wire representations.

Keyword
CMOS integrated circuits, circuit simulation, crosstalk, integrated circuit interconnections, integrated circuit modelling, 0.18 micron, CMOS process, capacitive crosstalk effects, circuit simulations, data-rate, on-chip interconnect latencies, power dissipation, wave pipelining
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13913 (URN)10.1109/NORCHP.2005.1597044 (DOI)
Available from: 2006-07-18 Created: 2006-07-18 Last updated: 2009-05-25
9. An On-Chip Delay- and Skew-Insensitive Multi-Cycle Comunication Scheme
Open this publication in new window or tab >>An On-Chip Delay- and Skew-Insensitive Multi-Cycle Comunication Scheme
2006 (English)In: International Solid-State Circuits Conference 2006, San Fransisco, USA, 2006Conference paper, Published paper (Other academic)
Abstract [en]

A synchronous latency-insensitive design (SLID) method that mitigates unknown on-chip global wire delays and removes the need for controlling global clock skew is presented. An SLID-based 5.4mm-long on-chip global bus, fabricated in a standard 0.18mum CMOS process, supports 3Gb/s/wire and accepts plusmn2 clock cycles of data-clock skew. This paper focuses on data synchronization for large global on-chip signals, which has become a difficult issue in high-frequency processor designs.

Keyword
CMOS integrated circuits, delays, integrated circuit design, integrated circuit interconnections, synchronisation, 0.18 micron, 5.4 mm, CMOS process, data synchronization, data-clock skew, global clock skew, multicycle communication, on-chip global wire delays, synchronous latency-insensitive design
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-13914 (URN)10.1109/ISSCC.2006.1696233 (DOI)1-4244-0079-1 (ISBN)
Available from: 2006-07-18 Created: 2006-07-18

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Caputa, Peter

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