Interfacing a processor core in FPGA to an audio system
Independent thesis Basic level (professional degree), 20 points / 30 hpStudent thesis
The thesis project consists on developing an interface for a Nios II processor integrated in a board of Altera (UP3- 2C35F672C6 Cyclone II).
The main goal is show how the Nios II processor can interact with the other components of the board.The Quartus II software has been used to create to vhdl code of the interfaces, compile it and download it into the board. The Nios II IDE tool is used to build the C/C++ files and download them into the processor.
It has been prepared an application for the audio codec integrated in the board (Wolfson WM8731 24-bit sigma-delta audio CODEC). The line input of the audio codec receives an analog signal from a laptop, this signal is managed by the control interface of the audio codec. The converters ADCs and DACs are stereo 24-bit sigma delta and they are used with oversampling digital interpolation and decimation filters.
The digital interface of the audio codec sends the digital signal to the Nios II processor and receives the data from the processor. After building the interfaces for the audio codec and the processor, it has been prepared an application in C++ language for the processor that modifies the volume of the signal.
The signal come back to the audio codec and it is possible to check the results with headphones or speakers at the line output of the audio codec.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2006. , 41 p.
Nios, audio CODEC, Quartus, SOPC bulider, IDE
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-7191ISRN: LiTH-ISY-EX--06/3896--SEOAI: oai:DiVA.org:liu-7191DiVA: diva2:22246
2006-06-07, Nollstället room, B-building, 09:15