Implementation and Design of a Bit-Error Generator and Logger for Multi-Gigabit Serial Links
Independent thesis Basic level (professional degree), 20 points / 30 hpStudent thesis
Test Tools are very important in the design of a system. They generally simulate a working environment, only at a higher
speed, or with less frequently occurring test cases. In the verification of protocols based on the Fibre Channel physical layer,
this becomes a necessity, as errors can be non-existent or very unusual in normal operating environments. Most systems need
to be able to handle these unexpected events nonetheless. Therefore, there is a need for a method of introducing these errors
in a controlled way.
A bit error generation and logging tool for two proprietary protocols based on the Fibre Channel physical layer has been
developed. The hardware platform consists mainly of a Virtex II Pro FPGA with accompanying I/O support. Control of the
hardware is handled by a graphical user interface residing on a PC. Communication between the hardware and the PC is
handled with a UART. The final implementation can handle four parallel one way links, or two full duplex links,
independently. This report describes the implementation and the necessary theoretical background for this.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2006. , 50 p.
Bit Error Generation, Fibre Channel, Implementation, FPGA, Virtex II Pro
IdentifiersURN: urn:nbn:se:liu:diva-7268ISRN: LiTH-ISY-EX--07/3928--SEOAI: oai:DiVA.org:liu-7268DiVA: diva2:22298
2007-01-19, Glashuset, B-huset, Ingång 25, Linköping, 08:15