Utilizing Process Variations for Reference Generation in a Flash ADC
2009 (English)In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, ISSN 1549-7747, Vol. 56, no 5, 364-368 p.Article in journal (Refereed) Published
This brief presents an experimental study on how to take advantage of the increasing process variations in nanoscale CMOS technologies to achieve small and low-power high-speed analog-to-digital converters (ADCs). Particularly, the need for a reference voltage generation network has been eliminated in a 4-bit Flash ADC in 90-nm CMOS, with small-sized comparators. The native comparator offsets, resulting from the process-variation-induced mismatch, are used as the only source of reference levels, and redundancy is used to acquire the desired resolution. The measured performance of the 1.5-GS/s ADC is comparable to traditional state-of-the art ADCs and dissipates 23 mW.
Place, publisher, year, edition, pages
2009. Vol. 56, no 5, 364-368 p.
Flash analog-to-digital converter (ADC), high-performance design, parameter variation
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-19138DOI: 10.1109/TCSII.2009.2019165OAI: oai:DiVA.org:liu-19138DiVA: diva2:223397