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DSP Platform Benchmarking: DSP Platform Benchmarking
Linköping University, Department of Electrical Engineering.
2009 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Benchmarking of DSP kernel algorithms was conducted in the thesis on a DSP processor for teaching in the course TESA26 in the department of Electrical Engineering. It includes benchmarking on cycle count and memory usage. The goal of the thesis is to evaluate the quality of a single MAC DSP instruction set and provide suggestions for further improvement in instruction set architecture accordingly. The scope of the thesis is limited to benchmark the processor only based on assembly coding. The quality check of compiler is not included. The method of the benchmarking was proposed by BDTI, Berkeley Design Technology Incorporations, which is the general methodology used in world wide DSP industry.

Proposals on assembly instruction set improvements include the enhancement of FFT and DCT. The cycle cost of the new FFT benchmark based on the proposal was XX% lower, showing that the proposal was right and qualified. Results also show that the proposal promotes the cycle cost score for matrix computing, especially matrix multiplication. The benchmark results were compared with general scores of single MAC DSP processors offered by BDTI.

Place, publisher, year, edition, pages
2009. , 57 p.
Keyword [en]
DSP, benchmark, benchmarking, FFT, IFFT, DCT, blocktransfer, Single FIR Filter, Matrix Multiplication, Crosscorrelation
National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-19258ISRN: LiTH-ISY-EX—09/4108—SEDOI: 09/4108OAI: diva2:223891
Subject / course
Master of Science in Electronics Design Engineering
2009-06-05, Glashuset, Glashuset, 25 entrance of B-building, Linkoping University, Glashuset, 15:15 (English)
Available from: 2009-06-15 Created: 2009-06-15 Last updated: 2011-09-21Bibliographically approved

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Xinyuan, Luo
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