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Embedded boundary scan for test & debug
Linköping University, Department of Computer and Information Science.
2009 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

The boundary scan standard which has been in existence since the early nineties is widely used to test printed circuit boards (PCB). It is primarily aimed at providing increased physical test access to surface mounted devices on printed circuit boards (PCB). Using boundary scan avoids using functional testing and In-circuit-techniques like 'bed of nails' for structurally testing PCBs as increasing densities and complexities made opting for them a herculean task. Though the standard has had a revolutionizing effect on board testing conducted during the development and production phases, there is a lack of a standardized mechanism to allow IEEE 1149.1 to be used in a system post installation. This has led to problems typically encountered during field test runs, like the issue of high number of No-Fault-Found (NFF), being left unaddressed. The solution lies in conducting a structural test after a given module has already been installed in the system. This can be done by embedding the programmability features of the boundary scan test mechanism into the Unit under test (UUT) thereby enabling the UUT to conduct boundary scan based self tests without the need of external stimuli. In this thesis, a test and debug framework, which aims to use boundary-scan in post system-installation, is the subject of a study and subsequent enhancement. The framework allows embedding much of the test vector deployment and debug mechanism onto the Unit under test (UUT) to enable its remote testing and debug. The framework mainly consists of a prototype board which, along with the UUT, comprise the 'embedded system'. The following document is a description of the phased development of above said framework and its intended usage in the field.

Place, publisher, year, edition, pages
2009. , 70 p.
Keyword [en]
boundary scan, JTAG, embedded, test
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-19368ISRN: LITH-EX-A--09/031--SEOAI: oai:DiVA.org:liu-19368DiVA: diva2:224721
Presentation
2009-06-01, Donald Knuth, B-house, IDA, Linköpings Universitet, Linköping, Sweden, 13:00 (English)
Uppsok
teknik
Supervisors
Examiners
Available from: 2009-06-22 Created: 2009-06-20 Last updated: 2009-06-22Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
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  • de-DE
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  • nn-NB
  • sv-SE
  • Other locale
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Output format
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