1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
2006 (English)In: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), 2006, 464-467 p.Conference paper (Refereed)
This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.
Place, publisher, year, edition, pages
2006. 464-467 p.
CMOS digital integrated circuits, clocks, electric noise measurement, integrated circuit noise, jitter
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-14044DOI: 10.1109/ESSCIR.2006.307481OAI: oai:DiVA.org:liu-14044DiVA: diva2:22519