A 24-mW, 0.02-mm2, 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS
2006 (English)In: Proceedings of the IEEE International System-on-Chip Conference (SoCC), 2006, 257-260 p.Conference paper (Other academic)
This paper presents a low-power small-area DLL-based frequency multiplier. Instead of using edge combiner-based clock synthesis scheme, the proposed frequency multiplier utilizes a ring oscillator, which is controlled by a DLL. An injection-locked slave ring oscillator is used for jitter suppression. The implementation of the proposed structure in 130-nm CMOS occupies an area of 0.02 mm2. It operates in the frequency range of 100 MHz to 1.5 GHz while consuming 24-mW power from a 1.2-V supply at 1.5 GHz. The measured output phase noise at 1.5 GHz is ¿100.1 dBc/Hz at a 4-MHz frequency offset.
Place, publisher, year, edition, pages
2006. 257-260 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-14045DOI: 10.1109/SOCC.2006.283893OAI: oai:DiVA.org:liu-14045DiVA: diva2:22520