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Circuit Techniques for On-Chip Clocking and Synchronization
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2006 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Today’s microprocessors with millions of transistors perform high-complexity computing at multi-gigahertz clock frequencies. The ever-increasing chip size and speed call for new methodologies in clock distribution network. Conventional global synchronization techniques exhibit many drawbacks in the advanced VLSI chips such as high-speed microprocessors. A significant percentage of the total power consumption in a microprocessor is dissipated in the clock distribution network. Also since the chip dimensions increase, clock skew management becomes very challenging in the framework of conventional methodology. Long interconnect delays limit the maximum clock frequency and become a bottleneck for future microprocessor design. In such a situation, new alternative techniques for synchronization in system-on-chip are demanded.

This thesis presents new alternatives for traditional clocking and synchronization methods, in which, speed and power consumption bottlenecks are treated. For this purpose, two new techniques based on mesochronous synchronization and resonant clocking are investigated. The mesochronous synchronization technique deals with remedies for skew and delay management. Using this technique, clock frequency up to 5 GHz for on-chip communication is achievable in 0.18-μm CMOS process. On the other hand the resonant clocking solves significant power dissipation problem in the clock network. This method shows a great potential in power saving in very large-scale integrated circuits. According to measurements, 2.3X power saving in clock distribution network is achieved in 130-nm CMOS process. In the resonant clocking, oscillator plays a crucial role as a clock generator. Therefore an investigation about oscillators and possible techniques for jitter and phase noise reduction in clock generators has been done in this research framework. For this purpose a study of injection locking phenomenon in ring oscillators is presented. This phenomenon can be used as a jitter suppression mechanism in the oscillators. Also a new implementation of the DLL-based clock generators using ring oscillators is presented in 130-nm CMOS process. The measurements show that this structure operates in the frequency range of 100 MHz-1.5 GHz, and consumes less power and area compared to the previously reported structures. Finally a new implementation of a 1.8-GHz quadrature oscillator with wide tuning range is presented. The quadrature oscillators potentially can be used as future clock generators where multi-phase clock is needed.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2006. , 58 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1241
Keyword [en]
Clocking-Synchronization-CMOS-Integrated Circuit
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-7505ISBN: 91-85497-44-4 (print)OAI: oai:DiVA.org:liu-7505DiVA: diva2:22522
Presentation
2006-04-11, Glashuset, House B, Campus Valla, Campus Valla, Linköpings universitet, 00:00 (English)
Opponent
Supervisors
Note
Report code: LiU-TEK-LIC-2006:22Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2009-03-30
List of papers
1. A New Mesochronous Clocking Scheme for Synchronization in SoC
Open this publication in new window or tab >>A New Mesochronous Clocking Scheme for Synchronization in SoC
2004 (English)In: Proceedings of the 2004 International Symposium on Circuits and Systems(ISCAS), 2004, Vol. 6, 605-608 p.Conference paper, Published paper (Refereed)
Abstract [en]

Future System-on-Chips (SoCs) need a new strategy for synchronization and clocking. In large-scale and high-speed systems, the traditional globally synchronous approach is not longer viable, due to severe wire delays. Instead new solutions as "Globally Asynchronous, Locally Synchronous" (GALS) approaches have been proposed. We propose to replace the GALS approach with a mesochronous clocking principle. In this paper we present such an approach together with a circuit solution in 0.18 μm CMOS process that allows clocking frequencies up to 5 GHz.

Series
, ISSN 1057-7122
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14042 (URN)
Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2009-05-27
2. A Study of Injection Locking in Ring Oscillators
Open this publication in new window or tab >>A Study of Injection Locking in Ring Oscillators
2005 (English)In: IEEE International Symposium on Circuits and Systems (ISCAS), 2005, Vol. 8, 5465-5468 p.Conference paper, Published paper (Refereed)
Abstract [en]

The paper presents an analysis of the injection locking phenomenon in CMOS ring oscillators. Adler's equation in injection locking is proved for a three-stage ring oscillator and the behavior of this kind of oscillator in the locked condition with respect to phase noise and jitter reduction has been analyzed.

Keyword
injection locking, ring oscillators, phase noise, jitter
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14043 (URN)10.1109/ISCAS.2005.1465873 (DOI)
Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2009-05-27Bibliographically approved
3. 1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
Open this publication in new window or tab >>1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
2006 (English)In: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), 2006, 464-467 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.

Keyword
CMOS digital integrated circuits, clocks, electric noise measurement, integrated circuit noise, jitter
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14044 (URN)10.1109/ESSCIR.2006.307481 (DOI)
Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2010-01-14Bibliographically approved
4. A 24-mW, 0.02-mm2, 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS
Open this publication in new window or tab >>A 24-mW, 0.02-mm2, 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS
2006 (English)In: Proceedings of the IEEE International System-on-Chip Conference (SoCC), 2006, 257-260 p.Conference paper, Published paper (Other academic)
Abstract [en]

This paper presents a low-power small-area DLL-based frequency multiplier. Instead of using edge combiner-based clock synthesis scheme, the proposed frequency multiplier utilizes a ring oscillator, which is controlled by a DLL. An injection-locked slave ring oscillator is used for jitter suppression. The implementation of the proposed structure in 130-nm CMOS occupies an area of 0.02 mm2. It operates in the frequency range of 100 MHz to 1.5 GHz while consuming 24-mW power from a 1.2-V supply at 1.5 GHz. The measured output phase noise at 1.5 GHz is ¿100.1 dBc/Hz at a 4-MHz frequency offset.

Keyword
CMOS
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-14045 (URN)10.1109/SOCC.2006.283893 (DOI)
Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2011-02-15Bibliographically approved
5. A Wide-Tuning Range 1.8 GHz Quadrature VCO Utilizing Coupled Ring Oscillators
Open this publication in new window or tab >>A Wide-Tuning Range 1.8 GHz Quadrature VCO Utilizing Coupled Ring Oscillators
2006 (English)In: Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2006, 5143-5146 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a fully integrated 1.8 GHz, 0.35-/spl mu/m CMOS quadrature voltage-controlled oscillator (QVCO) design. The topology uses coupled ring oscillators to produce quadrature outputs. In order to gain better phase noise performance LC-based filtering is introduced to QVCO. Also using variable inductance concept, a 1.2 GHz tuning range is achieved. According to simulation results, proposed QVCO draws 26.1 mA from 3.3V supply and exhibits a worst-case phase noise of -117.3 dBc/Hz at 1-MHz offset over the tuning range.

Keyword
quadrature VCO, tuning range, coupled ring oscillators, CMOS
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14046 (URN)10.1109/ISCAS.2006.1693790 (DOI)
Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2011-02-15Bibliographically approved

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