A Low Clock Load Conditional Flip-Flop
2004 (English)In: Proceedings of IEEE International System-on-Chip Conference, Santa Clara, California, USA, September 2004, 2004, 169-170 p.Conference paper (Other academic)
We describe a low clock load conditional transmission-gate flip-flop aimed at reducing on-chip clock power consumption. It utilizes a scalable and simple leakage compensation technique, which injects additional leakage current in opposite direction, thus compensating for the worst-case leakage. During any low frequency operation, the flip-flop is configured as a static flip-flop with increased functional robustness. Post-layout simulations show a 30 % clock power reduction compared to a conventional static flip-flop.
Place, publisher, year, edition, pages
2004. 169-170 p.
integrated circuit, low power, flip-flop, clock load
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-14065DOI: 10.1109/SOCC.2004.1362394OAI: oai:DiVA.org:liu-14065DiVA: diva2:22558