Low-Power Multi-GHz Circuit Techniques for On-chip Clocking
2006 (English)Licentiate thesis, comprehensive summary (Other academic)
The impressive evolution of modern high-performance microprocessors have resulted in chips with over one billion transistors as well as multi-GHz clock frequencies. As the silicon integrated circuit industry moves further into the nanometer regime, three of the main challenges to overcome in order for continuing CMOS technology scaling are; growing standby power dissipation, increasing variations in process parameters, and increasing power dissipation due to growing clock load and circuit complexity. This thesis addresses all three of these future scaling challenges with the overall focus on reducing the total clock-power for low-power, multi-GHz VLSI circuits.
Power-dissipation related to the clock generation and distribution is identified as the dominating contributor of the total active power dissipation. This makes novel power reduction techniques crucial in future VLSI design. This thesis describes a new energy-recovering clocking technique aimed at reducing the total chip clock-power. The proposed technique consumes 2.3x lower clock-power compared to conventional clocking at a clock frequency of 1.56 GHz.
Apart from increasing power dissipation due to leakage also the robustness constraints for circuits are impacted by the increasing leakage. To improve the leakage robustness for sub-90 nm low clock load dynamic flip-flops a novel keeper technique is proposed. The proposed keeper utilizes a scalable and simple leakage compensation technique. During any low frequency operation, the flip-flop is configured as a static flip-flop with increased functional robustness.
In order to compensate the impact of the increasingly large process variations on latches and flip-flops, a reconfigurable keeper technique is presented in this thesis. In contrast to the traditional design for worst-case process corners, a variable keeper circuit is utilized. The proposed reconfigurable keeper preserves the robustness of storage nodes across the process corners without degrading the overall chip performance.
Place, publisher, year, edition, pages
Institutionen för systemteknik , 2006. , 112 p.
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1240
CMOS, low-power, high-performance, flip-flop, clocking, leakage-compensation, process-variation
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-7545ISBN: 91-85497-39-8OAI: oai:DiVA.org:liu-7545DiVA: diva2:22562
2006-03-28, Glashuset, B-huset, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Larsson-Edefors, Per, Professor
Report code: LiU-TEK-LIC-2006:21.2006-10-092006-10-092010-01-14
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