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Low-Power Multi-GHz Circuit Techniques for On-chip Clocking
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2006 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

The impressive evolution of modern high-performance microprocessors have resulted in chips with over one billion transistors as well as multi-GHz clock frequencies. As the silicon integrated circuit industry moves further into the nanometer regime, three of the main challenges to overcome in order for continuing CMOS technology scaling are; growing standby power dissipation, increasing variations in process parameters, and increasing power dissipation due to growing clock load and circuit complexity. This thesis addresses all three of these future scaling challenges with the overall focus on reducing the total clock-power for low-power, multi-GHz VLSI circuits.

Power-dissipation related to the clock generation and distribution is identified as the dominating contributor of the total active power dissipation. This makes novel power reduction techniques crucial in future VLSI design. This thesis describes a new energy-recovering clocking technique aimed at reducing the total chip clock-power. The proposed technique consumes 2.3x lower clock-power compared to conventional clocking at a clock frequency of 1.56 GHz.

Apart from increasing power dissipation due to leakage also the robustness constraints for circuits are impacted by the increasing leakage. To improve the leakage robustness for sub-90 nm low clock load dynamic flip-flops a novel keeper technique is proposed. The proposed keeper utilizes a scalable and simple leakage compensation technique. During any low frequency operation, the flip-flop is configured as a static flip-flop with increased functional robustness.

In order to compensate the impact of the increasingly large process variations on latches and flip-flops, a reconfigurable keeper technique is presented in this thesis. In contrast to the traditional design for worst-case process corners, a variable keeper circuit is utilized. The proposed reconfigurable keeper preserves the robustness of storage nodes across the process corners without degrading the overall chip performance.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2006. , 112 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1240
Keyword [en]
CMOS, low-power, high-performance, flip-flop, clocking, leakage-compensation, process-variation
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-7545ISBN: 91-85497-39-8 (print)OAI: oai:DiVA.org:liu-7545DiVA: diva2:22562
Presentation
2006-03-28, Glashuset, B-huset, Campus Valla, Linköpings universitet, Linköping, 13:15 (English)
Opponent
Supervisors
Note
Report code: LiU-TEK-LIC-2006:21.Available from: 2006-10-09 Created: 2006-10-09 Last updated: 2010-01-14
List of papers
1. A Low Clock Load Conditional Flip-Flop
Open this publication in new window or tab >>A Low Clock Load Conditional Flip-Flop
2004 (English)In: Proceedings of IEEE International System-on-Chip Conference, Santa Clara, California, USA, September 2004, 2004, 169-170 p.Conference paper, Published paper (Other academic)
Abstract [en]

We describe a low clock load conditional transmission-gate flip-flop aimed at reducing on-chip clock power consumption. It utilizes a scalable and simple leakage compensation technique, which injects additional leakage current in opposite direction, thus compensating for the worst-case leakage. During any low frequency operation, the flip-flop is configured as a static flip-flop with increased functional robustness. Post-layout simulations show a 30 % clock power reduction compared to a conventional static flip-flop.

Keyword
integrated circuit, low power, flip-flop, clock load
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14065 (URN)10.1109/SOCC.2004.1362394 (DOI)
Available from: 2006-10-09 Created: 2006-10-09 Last updated: 2009-05-15
2. A Process Variation Tolerant Technique for sub-70 nm Latches and Flip-Flops
Open this publication in new window or tab >>A Process Variation Tolerant Technique for sub-70 nm Latches and Flip-Flops
2005 (English)In: Proceedings of the 23rd IEEE NORCHIP Conference, Oulu, Finland, November 2005, 2005, 149-152 p.Conference paper, Published paper (Other academic)
Abstract [en]

 

This paper describes a sub-70nm circuit technique

that compensates the impact of the increasingly large

process variations on latches and flip-flops. In contrast

to the traditional design for worst-case process corners,

we utilize a variable keeper circuit that preserves the

robustness of storage nodes across the process corners,

without degrading the overall chip performance. Power

and delay improvements of 7 % and 12 % respectively

have been observed for wide static MUX-latch circuits in

a 65nm CMOS technology. Moreover, the proposed

technique enables functional flip-flops with weak uninterrupted

keepers leading to over 9 % clock power

reduction.

Keyword
CMOS, process variation, keepers, latches, flip-flop, closk power
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14066 (URN)
Available from: 2006-10-09 Created: 2006-10-09 Last updated: 2009-05-18
3. Power-Performance Analysis of Sinusoidally Clocked Flip-Flops
Open this publication in new window or tab >>Power-Performance Analysis of Sinusoidally Clocked Flip-Flops
2005 (English)In: Proceedings of 23rd IEEE NORCHIP Conference, Oulu, Finland, November 2005, 2005, 153-156 p.Conference paper, Published paper (Other academic)
Abstract [en]

This paper can be viewed as a supplement to recent

interest in different on-chip resonant clocking

techniques. We present a study on the impact of

sinusoidal clock signals on power and performance of

six conventional flip-flops. The dominating effects are

delay penalties of 20-30 % for the best flip-flops, and

reduced race-margins. Two-phase master-slave flip-flops

and single-phase sense-amplifier flip-flops both obtain

robust timing behavior, and minimum power-delay

degradation.

Keyword
CMOS, flip-flop, sinusoidal clock, power-performance, resonant clocking
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14067 (URN)
Available from: 2006-10-09 Created: 2006-10-09 Last updated: 2009-05-15
4. 1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
Open this publication in new window or tab >>1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
2006 (English)In: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), 2006, 464-467 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.

Keyword
CMOS digital integrated circuits, clocks, electric noise measurement, integrated circuit noise, jitter
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-14044 (URN)10.1109/ESSCIR.2006.307481 (DOI)
Available from: 2006-10-05 Created: 2006-10-05 Last updated: 2010-01-14Bibliographically approved

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Hansson, Martin

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