liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Hardware Accelerator for Duo-binary CTC decoding: Algorithm Selection, HW/SW Partitioning and FPGA Implementation
Linköping University, Department of Electrical Engineering.
Linköping University, Department of Electrical Engineering.
2006 (English)Independent thesis Basic level (professional degree), 20 points / 30 hpStudent thesis
Abstract [en]

Wireless communication is always struggling with errors in the transmission. The digital data received from the radio channel is often erroneous due to thermal noise and fading. The error rate can be lowered by using higher transmission power or by using an effective error correcting code. Power consumption and limits for electromagnetic radiation are two of the main problems with handheld devices today and an efficient error correcting code will lower the transmission power and therefore also the power consumption of the device.

Duo-binary CTC is an improvement of the innovative turbo codes presented in 1996 by Berrou and Glavieux and is in use in many of today's standards for radio communication i.e. IEEE 802.16 (WiMAX) and DVB-RSC. This report describes the development of a duo-binary CTC decoder and the different problems that were encountered during the process. These problems include different design issues and algorithm choices during the design.

An implementation in VHDL has been written for Alteras Stratix II S90 FPGA and a reference-model has been made in Matlab. The model has been used to simulate bit error rates for different implementation alternatives and as bit-true reference for the hardware verification.

The final result is a duo-binary CTC decoder compatible with Alteras Stratix II designs and a reference model that can be used when simulating the decoder alone or the whole signal processing chain. Some of the features of the hardware are that block sizes, puncture rates and number of iterations are dynamically configured between each block Before synthesis it is possible to choose how many decoders that will work in parallel and how many bits the soft input will be represented in. The circuit has been run in 100 MHz in the lab and that gives a throughput around 50Mbit with four decoders working in parallel. This report describes the implementation, including its development, background and future possibilities.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2006. , 51 p.
Keyword [en]
Error Correcting Codes, Turbo Codes, Decoding, Implementation, FPGA
National Category
Telecommunications
Identifiers
URN: urn:nbn:se:liu:diva-7902ISRN: LiTH-ISY-EX--06/3875--SEOAI: oai:DiVA.org:liu-7902DiVA: diva2:22815
Presentation
2006-11-03, Algorithmen, B-huset, 13:00
Uppsok
teknik
Supervisors
Examiners
Available from: 2006-12-11 Created: 2006-12-11

Open Access in DiVA

fulltext(626 kB)2948 downloads
File information
File name FULLTEXT01.pdfFile size 626 kBChecksum MD5
67b511766a021d8d3ebc51da41f3b5674cc303202615f8cf2dc8be4f9006008d80af1372
Type fulltextMimetype application/pdf

By organisation
Department of Electrical Engineering
Telecommunications

Search outside of DiVA

GoogleGoogle Scholar
Total: 2948 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

urn-nbn

Altmetric score

urn-nbn
Total: 1815 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf