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Direct Digital Pulse Width Modulation for Class D Amplifiers
Linköping University, Department of Electrical Engineering.
2007 (English)Independent thesis Advanced level (degree of Magister), 20 points / 30 hpStudent thesis
Abstract [en]

Class D amplifiers are becoming increasingly popular in audio devices. The strongest reason is the high efficiency which makes it advantageous for portable battery-driven products.

Infineon Technologies is developing products in this area, and has recently filed a patent application regarding an implementation of a part of the class D amplifier. The aim of this Master’s thesis is to evaluate a digital open-loop implementation of a class D amplifier, using the pending patent solution, and discuss the differences from an analog closed-loop implementation.

The focus has been on generating a high resolution PWM signal with a relatively low clock frequency. To achieve this, a hybrid of a counter and a self-calibrating tapped delay-line are used as a pulse generator. A model of the pulse generator was developed which made it possible to study how sampling frequency and different types of quantization affected quality parameters such as THD and SNR. With the results from the model two systems were implemented and simulated in HDL and as circuit schematics.

The proposed digital open-loop class D amplifier was found to be useful in voice-band applications and for music. Since the open-loop structure suffers from poor rejection of power supply ripple, either error correction or a regulated power supply is needed. If much effort is put on the different parts of the amplifier the result can be really good but, depending on other constraints on the system, it may be simpler and less time consuming to use the analog circuit with feedback to achieve hi-fi quality.

In summary, the combination of a counter and a self-calibrating tapped delay-line as a pulse generator is very useful in high resolution low-power systems. To avoid errors the delay-line and calibration can be made very accurate but with the expense of higher power consumption and area. However, the technique benefits from the small and fast logic devices available in deep sub-micron process technologies, which may finally lead to an advantage in power consumption and cost over the closed-loop analog solution.

Place, publisher, year, edition, pages
Institutionen för systemteknik , 2007. , 78 p.
Keyword [en]
PWM, Class-D, delay-line, direct digital modulation, delay element
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-8476ISRN: LiTH-ISY-EX--07/3864--SEOAI: oai:DiVA.org:liu-8476DiVA: diva2:23244
Presentation
2007-01-22, Algoritmen, B, 58381, Linköping, 13:15
Uppsok
teknik
Supervisors
Examiners
Available from: 2007-03-07 Created: 2007-03-07

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CiteExportLink to record
Permanent link

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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf