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Improvement Potential and Equalization Example for Multidrop DRAM Memory Buses
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2009 (English)In: IEEE TRANSACTIONS ON ADVANCED PACKAGING, ISSN 1521-3323, Vol. 32, no 3, 675-682 p.Article in journal (Refereed) Published
Abstract [en]

For PC DRAM memory buses, the number of slots per channel have been decreased as signal frequencies increase. This limits the data capacity per channel. In this paper, we show that the slot reduction is not due to fundamental limits of the channel structure but due to signaling schemes. An equalization scheme is presented which enables higher bit-rates with minimum modification of bus structure and memory circuits. The circuitry added to the host side of the bus has reasonable complexity and features very low latency. Measurements of memory-to-host transmissions over a four-drop-bus at 2.6 Gb/s using a 0.13 mu m CMOS test-circuit is presented.

Place, publisher, year, edition, pages
2009. Vol. 32, no 3, 675-682 p.
Keyword [en]
Adaptive equalizers, channel capacity, DRAM, multidrop bus
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-20002DOI: 10.1109/TADVP.2009.2013818OAI: oai:DiVA.org:liu-20002DiVA: diva2:232464
Available from: 2009-08-24 Created: 2009-08-24 Last updated: 2009-08-24

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Fredriksson, HenrikSvensson, Christer

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