A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode
2009 (English)In: IEEE JOURNAL OF SOLID-STATE CIRCUITS, ISSN 0018-9200, Vol. 44, no 7, 1907-1913 p.Article in journal (Refereed) Published
This paper presents a low-power digital DLL-based clock generator. Once the DLL is locked, it operates in open-loop mode to reduce deterministic clock jitter and the power dissipation caused by DLL dithering. To keep track of any potential phase error introduced by environmental variations, a compensation mechanism is employed. In addition, a robust DLL-based frequency multiplication technique is proposed. The DLL-based clock generator is designed and fabricated in a 90 nm CMOS process in two different versions. Utilizing the proposed technique, the output jitter caused by DLL dithering is reduced significantly. Furthermore, the measured total power savings in the open-loop mode in comparison with the conventional closed-loop operation is about 14%.
Place, publisher, year, edition, pages
2009. Vol. 44, no 7, 1907-1913 p.
DLL dithering; DLL-based clock generator; frequency multiplier; low power; multiphase clock generator
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-20174DOI: 10.1109/JSSC.2009.2020229OAI: oai:DiVA.org:liu-20174DiVA: diva2:233681