Reduction of simultaneous switching noise in digital circuits
2006 (English)In: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, 187-190 p.Conference paper (Refereed)
In this paper the authors present results from measurements on a test chip used to evaluate our method for reduction of substrate noise that originates from the clock in digital circuits. The authors use long rise and fall times of the clock signal and a D flip-flop that operates well with this clock. With this approach, smaller clock buffers can be used, which results in smaller current peaks on the power supply lines and therefore less switching noise. The measured substrate noise on the test chip was reduced by 20% and up to 54%. With optimized clock buffers this method has a potential of an even larger noise reduction.
Place, publisher, year, edition, pages
2006. 187-190 p.
CMOS integrated circuits, buffer circuits, clocks, flip-flops, integrated circuit noise, integrated circuit testing
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-14445DOI: 10.1109/NORCHP.2006.329207ISBN: 1-4244-0772-9OAI: oai:DiVA.org:liu-14445DiVA: diva2:23514