Introduction to substrate noise in SOI CMOS integrated circuits
2005 (English)In: Proc. National Conf. on Radio Science, RVK'05, 2005Conference paper (Other academic)
In this paper an introduction to substrate noise in silicon oninsulator (SOI) is given. Differences between substratenoise coupling in conventional bulk CMOS and SOICMOS are discussed and analyzed by simulations. The efficiencyof common substrate noise reduction methods arealso analyzed. Simulation results show that the advantageof the substrate isolation in SOI is only valid up to a frequencythat highly depends on the chip structure. In bulk,guard bands are normally directly connected to the substrate.In SOI, the guard bands are coupled to the substratevia the parasitic capacitance of the silicon oxide. Therefore,the efficiency of a guard may be much larger in aconventional bulk than in SOI. One opportunity in SOI isthat a much higher resistivity of the substrate can be used,which results in a significantly higher impedance up to afrequency where the coupling is dominated by the capacitivecoupling of the substrate.
Place, publisher, year, edition, pages
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-14447OAI: oai:DiVA.org:liu-14447DiVA: diva2:23516