Reduction of simultaneous switching noise in analog signal band
2007 (English)In: Proc. IEEE European Conf. Circuit Theory and Design, ECCTD'07, 2007, 148-151 p.Conference paper (Refereed)
In this work we focus on reducing the simultaneous switching noise located in the frequency band from DC up to half of the digital clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. We use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 mum CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB when using the proposed method. The cost is an increase in power consumption of almost a factor of three and a higher transistor count.
Place, publisher, year, edition, pages
2007. 148-151 p.
CMOS integrated circuits, adders, flip-flops, frequency-domain analysis, mixed analog-digital integrated circuits, analog signal band, digital clock frequency, frequency components, frequency domain, higher transistor count, pipelined adders, precharged differential cascode switch logic, static CMOS logic, switching noise reduction, transistor level
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-14449DOI: 10.1109/ECCTD.2007.4529558ISBN: 978-1-4244-1341-6OAI: oai:DiVA.org:liu-14449DiVA: diva2:23518