Design methodology for memory-efficient multi-standard baseband processors
2005 (English)In: Asia Pacific Communication Conference, Perth, Australia, 2005, 28-32 p.Conference paper (Other academic)
Efficient programmable baseband processors are important in order to enable true multi-standard radio platforms and software defined radio systems. In programmable processors, the memory sub-system accounts for a large part of both the area and power consumption. This paper presents a methodology for designing memory efficient multi-standard baseband processors. The methodology yields baseband processor micro-architectures, which eliminate excessive data moves between memories while still allowing true flexibility by utilizing SIMD clusters connected to memory banks via an internal network. The methodology has successfully been used to create a multi-standard baseband processor for OFDM-based wireless standards. This paper discusses the IEEE 802.16e (WiMAX), DVB-H (digital video broadcast - handheld) and DAB (digital audio broadcast) standards. The architecture is truly scalable to accommodate future OFDM systems. Scheduling and resource allocation show that with the proposed memory structure and architecture, the processor can manage the baseband functions of the described standards operating at 80 MHz and using only 28k words of memory.
Place, publisher, year, edition, pages
2005. 28-32 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-14522DOI: 10.1109/APCC.2005.1554012ISBN: 0-7803-9132-2OAI: oai:DiVA.org:liu-14522DiVA: diva2:23635
2005 Asia-Pacific Conference on Communications (APCC). 3-5 October, 2005. Perth, Australia.