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A fully programmable Rake-receiver architecture for multi-standard baseband processors
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2005 (English)In: Proceedings of the Intl. conference on Networks and Communication systems, NCS2005, 2005, 292-297 p.Conference paper, Published paper (Other academic)
Abstract [en]

Programmability will be increasingly important in future multi-standard radio systems. We are presenting a fully programmable and flexible DSP platform capable of efficiently performing channel estimation and Maximum Ratio Combining (MRC) based channel equalization for a large number of wireless transmission systems in software. Our processor is based on a programmable DSP processor with SIMD-computing clusters. We also map Rake receiver kernel functions supporting a large number of commonWireless LAN and 3G standards to this microarchitecture. The use of the inherit flexibility for future standards is also discussed. Benchmarking show that with the proposed instruction set architecture, our architecture can support channel estimation, equalization and decoding of: WCDMA (FDD/TDD-modes), TD-SCDMA and the higher data rates of IEEE 802.11b (CCK) at clock frequency not exceeding 76 MHz.

Place, publisher, year, edition, pages
2005. 292-297 p.
Keyword [en]
CDMA, Rake, MRC, DSP, SDR
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-14524OAI: oai:DiVA.org:liu-14524DiVA: diva2:23637
Conference
The Intl. conference on Networks and Communication systems, NCS2005. Krabi, Thailand 2005.
Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2013-11-06
In thesis
1. Design of multi-standard baseband processors
Open this publication in new window or tab >>Design of multi-standard baseband processors
2005 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Efficient programmable baseband processors are important in order to enable true multi-standard radio platforms and software defined radio systems. The ever changing wireless network industry also requires flexible and versatile baseband processors to be able to adapt quickly to new and updated standards. The convergence of mobile communication devices and systems require multi-standard capabilities in the processing devices. The processors do not only need the capability to handle differences in a single standard, often there is a great need to cover several completely different modulation methods such as OFDM, CDMA and single carrier modulation with the same processing device. All this requires a programmable baseband processor because a pure fixed-function ASIC solution is not flexible enough. Furthermore, ASIC solutions for multi-standard baseband processing are less area efficient than their programmable counterparts since processing resources cannot efficiently be shared between different operations and standards. This project was initiated for the above mentioned reason as a continuation of a previous baseband processor project at the research group. Accordingly, this thesis is devoted to the design of area efficient, low clock rate, fully programmable baseband processors. A reduction of the clock rate will simplify the design of the processor as well as save power in the application. Since most multi-standard processing devices will be used in a mobile environment, low power is essential. Normally, extra computing resources must be added to a system designed for low clock rate operation compared to a regular solution, resulting in a higher area and complexity of the chip. In this project effort has been made to create efficient base architectures maintaining a low area and clock rate while also maintaining flexibility and processing capability. At the same time design methods for the required DSP execution units within the processor have been developed.

Usually general baseband processing includes many tasks such as error control coding/ decoding, interleaving, scrambling etc, however in this thesis because of time and resource limitations, the focus is on the symbol related processing, although the bit manipulation and forward error correction tasks are also studied regarding acceleration.

Publisher
56 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1173
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-30479 (URN)16053 (Local ID)91-85299-69-3 (ISBN)16053 (Archive number)16053 (OAI)
Presentation
2005-06-08, Sal Visionen, Linköpings universitet, Linköping, 14:15 (Swedish)
Opponent
Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-06

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Nilsson, AndersTell, EricLiu, Dake

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