An accelerator structure for programmable multi-standard baseband processors
2004 (English)In: Proceedings of the Intl. conference on Wireless networks and Emerging technologies, WNET2004 / [ed] A.O. Fapojuwo, 2004, 644-649 p.Conference paper (Other academic)
Programmability will be increasingly important in future multi-standard radio systems. We are proposing an archi tecture for fully programmable baseband processing, based on a programmable DSP processor and a number of config urable accelerators which communicate via a configurable network. Acceleration of common cycle-consuming DSP jobs is necessary in order to manage wide-band modula tion schemes. In this paper we investigate which jobs are suitable for acceleration in a programmable baseband proc sessor supporting a number of common Wireless LAN and 3G standards. Simulations show that with the proposed set of accelerators, our architecture can support the discussed standards, including IEEE 802.11a 54 Mbit/s wireless LAN reception, at a clock frequency not exceeding 120 MHz.
Place, publisher, year, edition, pages
2004. 644-649 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-14525ISBN: 0-88986-403-9OAI: oai:DiVA.org:liu-14525DiVA: diva2:23638
Wireless Networks and Emerging Technologies(WNET 2004) July 8 – 10, 2004. Banff, Canada.